Zobrazeno 1 - 10
of 80
pro vyhledávání: '"Nandy SK"'
Autor:
Sosio, M, Donadio, S, Maffioli, S, Monciardini, P., Bibb, MJ, Fernandez, L, Eliasson Lanz, A, Nandy, SK, Sahl, HG, Münch, D, Wohlleben, W, Bera, A, Pozzi, R, Stegmann, E, Walter, K, Xaiz, R, Busiello, I, Nespoli, A., PUGLIA, Anna Maria, ALDUINA, Rosa, GALLO, Giuseppe, GIARDINA, Anna
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od______3658::0684c6063b69d54910cdbdc23514e074
http://hdl.handle.net/10447/96037
http://hdl.handle.net/10447/96037
Publikováno v:
IndraStra Global.
In this paper we develop compilation techniques for the realization of applications described in a High Level Language (HLL) onto a Runtime Reconfigurable Architecture. The compiler determines Hyper Operations (HyperOps) that are subgraphs of a data
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=issn23813652::c3bdb294292347358cb3227e0980c4eb
https://igi.indrastra.com/items/show/202181
https://igi.indrastra.com/items/show/202181
Publikováno v:
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).
Processing streaming media comprises several program phases (often distinct) that are periodic and independent of application data. Here we characterize execution of such programs into execution phases based on their dynamic IPC (instruction per cycl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0a2f1f334279be5727e755062a0f04f3
https://doi.org/10.1109/aspdac.2004.1337605
https://doi.org/10.1109/aspdac.2004.1337605
Publikováno v:
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).
We study the delays faced by instructions in the pipeline of a superscalar processor and its impact on power and performance. Instructions that are ready-on-dispatch (ROD) are normally delayed in the issue stage due to resource constraints even thoug
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d4a331372fb776d2269bea8d52ef0a23
https://doi.org/10.1109/aspdac.2004.1337604
https://doi.org/10.1109/aspdac.2004.1337604
Publikováno v:
Proceedings. 15th Symposium on Integrated Circuits and Systems Design.
VLIW processors are statically scheduled processors and their performance depends on the quality of schedules generated by the compiler's scheduler. We propose a multi-threaded architectural support for speculative trace scheduling in VLIW processors
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a4893bc3b5371bb30a20bc166da05f88
https://doi.org/10.1109/sbcci.2002.1137635
https://doi.org/10.1109/sbcci.2002.1137635
Autor:
Rao, Pradeep H, Nandy, SK
Publikováno v:
IndraStra Global.
Statically scheduled processors are known to enable low complexity hardware implementations that lead to reduced design and verification time. However, statically scheduled processors are critically dependent on the compiler to exploit instruction le
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::f0c7fc58ed539601b0e24820564fbfd4
https://igi.indrastra.com/items/show/187182
https://igi.indrastra.com/items/show/187182
Autor:
Lele, Abhijit M, Nandy, SK
Multistage switch interconnects like banyan switches are preferred in high speed networks for their cascadable structure and suitability for VLSI implementation. However most of these switch implementations are monolithic in nature and do not provide
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______182::20ad340e99bde00690923f1614541032
http://eprints.iisc.ernet.in/5360/
http://eprints.iisc.ernet.in/5360/
ASICs offer the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target archi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______182::099d8db34107aadc2149123164e3b37e
http://eprints.iisc.ernet.in/5866/
http://eprints.iisc.ernet.in/5866/
Autor:
Balakrishnan, S, Nandy, SK
Current day general purpose processors have been enhanced with what is called “media instruction set to achieve performance gains in applications that are media processing intensive. The instruction set that has been added exploits the fact that me
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______182::6eb97531bbdaa3819a55b24c7344b17a
http://eprints.iisc.ernet.in/6217/
http://eprints.iisc.ernet.in/6217/
Publikováno v:
IndraStra Global.
The routing of nets or a set of interconnection points is a complete intensive application encountered in CAD for VLSI design. This paper proposes a gridless algorithm for area routing based on the Hightower's Maze routing algorithm for message passi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=issn23813652::06a83a052591a08d4a5b290b770a3ea9
https://igi.indrastra.com/items/show/187530
https://igi.indrastra.com/items/show/187530