Výsledky vyhledávání - "Nan-Chun Lien"

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips

Publikováno v: IEEE Journal of Solid-State Circuits. 56:2817-2831

This article presents a computing-in-memory (CIM) structure aimed at improving the energy efficiency of edge devices running multi-bit multiply-and-accumulate (MAC) operations. The proposed scheme includes a 6T SRAM-based CIM (SRAM-CIM) macro capable

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::eec762d8b2cffbcc9800b0ea70d3f913
https://doi.org/10.1109/jssc.2021.3073254

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A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist

Autor: Yong Jyun Hu, Wei Hwang, Paul Sen Kan, Ming-Hsien Tu, Ching-Te Chuang, Chen Chien Hen, Li Wei Chu, Yang Hao I, Shyh-Jye Jou, Nan Chun Lien

Publikováno v: IEEE Transactions on Circuits and Systems I: Regular Papers. 61:3416-3425

This paper presents a cross-point 512 kb 8 T pipeline static random-access memory (SRAM). The cross-point structure eliminates write half-select disturb to facilitate bit-interleaving architecture for enhanced soft error immunity. The design employs

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6831aec55e7eb966d6c5c6aa1f0bf99d
https://doi.org/10.1109/tcsi.2014.2336531

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Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation

Autor: Ching-Te Chuang, Nan-Chun Lien, Wen-Rong Wu

Publikováno v: SoCC

This work proposes a novel Dual-Port (DP) 8T SRAM operation scheme. The scheme improves the Read stability and Write-ability, and allows asynchronous operation with arbitrary clock timing skew between two ports. It facilitates high performance, low-p

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2b585bf926f21373b1a8ae6c8468f5e4
https://doi.org/10.1109/socc.2013.6749669

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A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

Autor: Chi-Shin Chang, Shyh-Jye Jou, Cheng-Yo Cheng, Nan-Chun Lien, Hao-I Yang, Wei-Chiang Shih, Paul-Sen Kan, Chien-Hen Chen, Wei-Nan Liao, Yi-Wei Lin, Jian-Hao Wang, Ming-Hsien Tu, Ching-Te Chuang, Kuen-Di Lee, Yong-Jyun Hu, Wei Hwang, Wei-Chang Wang, Chia-Cheng Chen, Huan-Shun Huang

Publikováno v: ISCAS

We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Wr

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cd08d04ceaf2c5ba11e243a1a6b088e9
https://doi.org/10.1109/iscas.2013.6572134

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Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM

Autor: Yi-Wei Chiu, Ching-Te Chuang, Wei-Chiang Shih, Geng-Cing Lin, Yi-Wei Lin, Shyh-Jye Jou, Ming-Chien Tsai, Jyun-Kai Chu, Kuen-Di Lee, Shao-Cheng Wang, Nan-Chun Lien

Publikováno v: APCCAS

We present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps ∼ 32ns

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::409ee698e513be44c33be204108b203b
https://doi.org/10.1109/apccas.2012.6418985

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A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist

Autor: Wei Hwang, Hao-I Yang, Wen-Ta Lee, Ya-Ping Wu, Mao-Chih Hsia, Kuen-Di Lee, Nan-Chun Lien, Wei-Chiang Shih, Chih-Chiang Hsu, Yi-Wei Lin, Yung-Wei Lin, Ching-Te Chuang, Chien-Hen Chen

Publikováno v: SoCC

This paper describes an area-efficient variation-tolerant data-aware dynamic supply Write-assist scheme for a cross-point 8T SRAM. A 128Kb test chip implemented in 55nm Standard Performance CMOS technology achieves error free full functionality witho

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cdb580b12784ad5ad8d31965c036de88
https://doi.org/10.1109/socc.2012.6398351

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High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder

Autor: Wei-Chiang Shih, Mao-Chih Hsia, Yin-Nien Chen, Nan-Chun Lien, Chi-Shin Chang, Shyh-Jye Jou, Chih-Chiang Hsu, Geng-Cing Lin, Wen-Ta Lee, Kuen-Di Lee, Hung-Yu Li, Hao-I Yang, Wei Hwang, Ya-Ping Wu, Ching-Te Chuang, Yi-Wei Lin

Publikováno v: ISCAS

This paper presents a 1.0Mb high-performance 0.6V V MIN 6T SRAM design implemented in UMC 55nm Standard Performance (SP) CMOS technology. This design utilizes an adaptive LBL bleeder technique to reduce Read disturb and Half-Select disturb of 6T cell

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a9a7eb1899f6ddba2df6509dbb893b98
https://doi.org/10.1109/iscas.2012.6271624

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An all-digital bit transistor characterization scheme for CMOS 6T SRAM array

Autor: Ching-Te Chuang, Shyh-Jye Jou, Kuen-Di Lee, Jyun-Kai Chu, Ming-Chien Tsai, Yi-Wei Lin, Wei-Chiang Shih, Nan-Chun Lien, Geng-Cing Lin, Shao-Cheng Wang

Publikováno v: ISCAS

We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (V TH ) of 6T SRAM bit cell transistors (holding PM

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::52b6f8f1a61329c982938d55c2ca0bad
https://doi.org/10.1109/iscas.2012.6271804

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An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array

Autor: Shyh-Jye Jou, Yi-Wei Lin, Shao-Cheng Wang, Ching-Te Chuang, Ming-Chien Tsai, Nan-Chun Lien, Geng-Cing Lin, Hao-I Yang, Kuen-Di Lee, Wei-Chiang Shih, Wei Hwang

Publikováno v: VLSI-DAT

We present an all-digital Read Stability and Write Margin (WM) characterization scheme for CMOS 6T SRAM array. The scheme measures the cell Read Disturb voltage (V read ) and cell Inverter Trip voltage (V trip ) in SRAM cell array environment. Measur

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cc39580d8dc3f885ab3f35f51bd74256
https://doi.org/10.1109/vlsi-dat.2012.6212589

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