Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Nam-Jong Kim"'
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 68:2409-2413
A duo-binary signaling has been applied to both transmitter and receiver for high-speed low-power DRAM interface. The transmitter consists of a half-rate voltage-mode time-interleaved mixing duo-binary driver and a 2-tap feed-forward equalizer. The v
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c09d7807f6bb8ecfbbdc4ad6d372f7a8
https://doi.org/10.1109/tcsii.2021.3050823
https://doi.org/10.1109/tcsii.2021.3050823
Autor:
Nam Jong Kim
Publikováno v:
International Business Journal. 27:1-54
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::571d92290eb400c026ee46884bb31b77
https://doi.org/10.14365/ibj.2016.27.3.1
https://doi.org/10.14365/ibj.2016.27.3.1
Autor:
Nam Jong Kim, Alexander Schiller
Publikováno v:
SSRN Electronic Journal.
The popular assumption based on complete markets that the log of real exchange rate growth equals the difference between the logs of home and foreign IMRSs imposes a tight restriction on explaining the joint behavior of asset prices, exchange rates,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e8ac64f1cac70fcb03a598fabc8a70fe
https://doi.org/10.2139/ssrn.2797682
https://doi.org/10.2139/ssrn.2797682
Autor:
Hongil Yoon, Tae-Sung Jung, Chang-Ho Lee, Gi-Won Cha, Kyu-Nam Lim, Nam-jong Kim, Hongsik Jeong, Soo In Cho, Jun-Young Jeon, Kinam Kim, Keum-Yong Kim, Changsik Yoo, Tae-Young Chung, Kyu-Chan Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 34:1589-1599
A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-/spl mu/m CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d34fdcb9015f383af35f8e4eab34d1a1
https://doi.org/10.1109/4.799867
https://doi.org/10.1109/4.799867
Autor:
Soo-In Cho, Hongil Yoon, Sang-Bo Lee, Keum-Yong Kim, Byung-sik Moon, Kyu-Chan Lee, Nam-jong Kim, Chang-Hyun Kim, Jung-Hwa Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:779-786
A prototype 1 Gbit synchronous DRAM with independent subarray-controlled isolation and hierarchical decoding schemes is demonstrated to alleviate the difficulties encountered in high-density devices with regard to failure analysis and performance opt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00387051ce93a22363e0e9a3d9ac238a
https://doi.org/10.1109/4.668993
https://doi.org/10.1109/4.668993
Autor:
Jai-Hoon Sim, Kyu-Chan Lee, Nam-jong Kim, Soo-In Cho, Hongil Yoon, Byung-sik Moon, Dong-ryul Ryu, Seung-Moon Yoo, Changhyun Kim, Sang-Bo Lee, Keum-Yong Kim, Jei-Hwan Yoo
Publikováno v:
IEEE Journal of Solid-State Circuits. 32:642-648
This paper describes several new circuit design techniques for low V/sub CC/ regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (/spl Delta/V/sub BL/) as well as the V/sub GS/ margin by boosti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c07d12644c9745a83e883124a2740643
https://doi.org/10.1109/4.568824
https://doi.org/10.1109/4.568824
Autor:
Kyu Nam Lim, Nam Jong Kim, Chang-Ho Lee, Jun Young Jeon, Tae Young Jeong, Soo In Cho, Gi Won Cha, Keum Yong Kim, Ki Nam Kim, Hongil Yoon, Tae-Sung Jung, Hongsik Jeong, Kyu Chan Lee, Changsik Yoo
Publikováno v:
1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
While on-chip data flight times approach a few tens of nanoseconds for gigabit-scale DRAMs, a bandwidth over 250 MHz requires data input and output timing accuracy within 0.3 ns. Although a high-speed data interface can be achieved using precise cloc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64d34f7a4e5c767737d684d5b40c39cd
https://doi.org/10.1109/isscc.1999.759327
https://doi.org/10.1109/isscc.1999.759327
Autor:
Keum Yong Kim, Nam Jong Kim, Hyun Lee, Dong Il Seo, Jae-Yoon Sim, Hongsik Jeong, Byung Il Ryu, Jaeyoung Lee, Chang Gyu Hwang, Kyu Nam Lim, Sang Man Byun, Chang Hyun Choi, Won Suk Yang, Jel Hwan Yoo, Kinam Kim, Hongil Yoon
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
A 1.8 V 4 Gb DDR SDRAM for low voltage and high speed at full density has reduced inter-bitline coupling noise in the twisted open bit line architecture. Amplifier sensitivity and sensing margin are improved by gain-controlled pre-sensing and active
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::affd722f4694e8b6123a9b3310a3bd0d
https://doi.org/10.1109/isscc.2001.912681
https://doi.org/10.1109/isscc.2001.912681
Autor:
Kyuchan Lee, Changhyun Kim, Hongil Yoon, Keum-Yong Kim, Byung-Sik Moon, Sang-Bo Lee, Jung-Hwa Lee, Nam-Jong Kim, Soo-In Cho
Publikováno v:
IEEE Journal of Solid-State Circuits; 1998, Vol. 33 Issue 5, p779-786, 8p
Autor:
Kyuchan Lee, Changhyun Kim, Dong-Ryul Ryu, Jai-Hoon Sim, Sang-Bo Lee, Byung-Sik Moon, Keum-Yong Kim, Nam-Jong Kim, Seung-Moon Yoo, Hongil Yoon, Jei-Hwan Yoo, Soo-In Cho
Publikováno v:
IEEE Journal of Solid-State Circuits; 1997, Vol. 32 Issue 5, p642-648, 7p