Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Nalamalpu Ankireddy"'
Autor:
Nalamalpu Ankireddy, Fabrice Paillet, Chris Mozak, Gerhard Schrom, Nasser A. Kurd, Boyd Phelps, Ashish Khanna, Jonathan P. Douglas, Anant Deval
Publikováno v:
VLSIC
Intel Core™ M and 5th generation of Core™ processors (code named Broadwell) are fabricated on an optimized 14 nm process technology node resulting in a 49% reduction in feature-neutral die area. 14nm created a new optimized process flavor for Cor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14307945f50dafb736f38a0028b68661
https://doi.org/10.1109/vlsic.2015.7231304
https://doi.org/10.1109/vlsic.2015.7231304
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21:50-62
Trends in complementary metal-oxide-semiconductor (CMOS) technology and very large scale integration architectures are causing interconnect to play an increasing role in overall performance, power consumption, and design effort. Traditionally, repeat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f221c7cd5e98e7728ff165a0da2037f1
https://doi.org/10.1109/43.974137
https://doi.org/10.1109/43.974137
Autor:
Nasser A. Kurd, Srinivas Chennupaty, Timothy M. Wilson, Thomas P. Thomas, Mahmoud Elassal, Nalamalpu Ankireddy, Raghavan Kumar, Muntaquim Chowdhury, Christopher P. Mozak, Gomes Wilfred, Manoj B. Lal, Edward A. Burton, Matthew C. Merten, Anant Deval, Brent R. Boswell, Jonathan P. Douglas
Publikováno v:
ISSCC
The 4th Generation Intel® Core™ processor, codenamed Haswell, is a family of products implemented on Intel 22nm Tri-gate process technology [1]. The primary goals for the Haswell program are platform integration and low power to enable smaller for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::835b26ccfe92977402ef793590fb4da9
https://doi.org/10.1109/isscc.2014.6757361
https://doi.org/10.1109/isscc.2014.6757361
Autor:
Wayne Burleson, Nalamalpu Ankireddy
Publikováno v:
Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).
Repeaters are now widely used to increase the performance of long on-chip interconnections in CMOS VLSI. Significantly high power consumption and area overhead due to optimal repeater insertion will soon be a bigger problem with the number of on-chip
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f1c7c85db4c9ebe139b5efcf02267c5d
https://doi.org/10.1109/asic.2001.954689
https://doi.org/10.1109/asic.2001.954689
Autor:
Nalamalpu Ankireddy, Wayne Burleson
Publikováno v:
ISCAS
Repeaters are now widely used to increase the performance of long on-chip interconnections in CMOS VLSI. In this paper, we take an updated look at repeater insertion in state-of-the-art CMOS, using a new more detailed model. In spite of the more comp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7793a0482bedd5dd275fc3c0bbc04fe8
https://doi.org/10.1109/iscas.2000.856173
https://doi.org/10.1109/iscas.2000.856173
Autor:
Nalamalpu, Ankireddy, Burleson, Wayne
Publikováno v:
Proceedings of the 2001 International Symposium: Physical Design; 4/ 1/2001, p204-211, 8p
Autor:
Kurd, Nasser, Chowdhury, Muntaquim, Burton, Edward, Thomas, Thomas P., Mozak, Christopher, Boswell, Brent, Lal, Manoj, Deval, Anant, Douglas, Jonathan, Elassal, Mahmoud, Nalamalpu, Ankireddy, Wilson, Timothy M., Merten, Matthew, Chennupaty, Srinivas, Gomes, Wilfred, Kumar, Rajesh
Publikováno v:
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC); 2014, p112-113, 2p