Zobrazeno 1 - 10
of 64
pro vyhledávání: '"Nak-Woong Eum"'
Publikováno v:
IEIE Transactions on Smart Processing and Computing. 4:71-77
Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-po
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::068154f6269ccfc2247bd9b6321bdede
https://doi.org/10.5573/ieiespc.2015.4.2.071
https://doi.org/10.5573/ieiespc.2015.4.2.071
Publikováno v:
ICCE-Berlin
A future video codec processor will have to adopt the newly standardized High Efficiency Video Coding (HEVC/H.265) in a short time due to the limit of H.264's coding efficiency for large sized UHD images. This paper combines our designed decoder and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ddc5f2e8f939149b1ffc9e4b2a52d80
https://doi.org/10.1109/icce-berlin.2016.7684727
https://doi.org/10.1109/icce-berlin.2016.7684727
Autor:
Young-Su Kwon, Nak-Woong Eum
Publikováno v:
Journal of Circuits, Systems and Computers. 19:1435-1447
Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory sy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c323b163145423d3061b7da9da11b9bb
https://doi.org/10.1142/s0218126610006748
https://doi.org/10.1142/s0218126610006748
Autor:
Nak-Woong Eum, Young-Su Kwon
Publikováno v:
Microprocessors and Microsystems. 34:1-13
The advancement of process technology enables the integration of multiple cores featuring parallel processing of several tasks in a single die. The requirement of extensive memory bandwidth puts a major performance bottleneck in the multi-core archit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20e0cc4ea92c03ec9ad1d09c260ccd3a
https://doi.org/10.1016/j.micpro.2009.10.002
https://doi.org/10.1016/j.micpro.2009.10.002
Publikováno v:
ETRI Journal. 31:795-802
This paper presents the design of an advanced terrestrial digital multimedia broadcasting (AT-DMB) baseband receiver SoC. The AT-DMB baseband is incorporated into a hierarchical modulation scheme consisting of high priority (HP) and low priority (LP)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b29ee7052e3a8174ce4d083cca0c9be4
https://doi.org/10.4218/etrij.09.1209.0009
https://doi.org/10.4218/etrij.09.1209.0009
Publikováno v:
ETRI Journal. 31:732-740
This paper describes the implementation of a digital audio effect system-on-a-chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect alg
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1c5ed41388fb0641be6d73d2f5e3c296
https://doi.org/10.4218/etrij.09.1209.0029
https://doi.org/10.4218/etrij.09.1209.0029
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 14:1-23
A dynamic monitoring of thermal behavior of hardware resources using thermal sensors is very important to maintain the operation of systems safe and reliable. This article addresses the problem of thermal sensor allocation and placement for reconfigu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::39fc016ae5a336ab1236d095bc968d4d
https://doi.org/10.1145/1562514.1562518
https://doi.org/10.1145/1562514.1562518
Publikováno v:
VLSI-SoC
This paper proposes a virtual prototype based on the Aldebaran CPU core developed independently by ETRI. The virtual prototype provides instruction and function profiling functionality for software optimization as well as standard integration emulati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bea7af7aedd76f13633ce1dc43d11bb2
https://doi.org/10.1109/vlsi-soc.2015.7314434
https://doi.org/10.1109/vlsi-soc.2015.7314434
Publikováno v:
VLSI-SoC
We proposed an efficient VLSI hardware architecture of the High Efficiency Video Coding (HEVC) using a hybrid embedded compression algorithm for reducing the frame memory bandwidth. This architecture was designed to reduce the memory bandwidth using
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::32f5b2b9af1b8d6f6917e53694fbaef4
https://doi.org/10.1109/vlsi-soc.2015.7314432
https://doi.org/10.1109/vlsi-soc.2015.7314432
Publikováno v:
IEEE Transactions on Computers. 53:829-842
We present a new performance and routability driven routing algorithm for symmetrical array-based field-programmable gate arrays (FPGAs). A key contribution of our work is the overcoming of one essential limitation of the previous routing algorithms:
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a88f10f56bef1763eeab1b4802ed6815
https://doi.org/10.1109/tc.2004.20
https://doi.org/10.1109/tc.2004.20