Zobrazeno 1 - 8
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pro vyhledávání: '"Nainesh Agarwal"'
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783319691541
ISDDC
ISDDC
Domain generation algorithm (DGA) represents a safe haven for modern botnets, as it enables them to escape detection. Due to the fact that DGA domains are generated randomly, they tend to be unusually long, which can be leveraged toward detecting the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c263c79dd6fe3b8447b9e4d4327b1535
https://doi.org/10.1007/978-3-319-69155-8_2
https://doi.org/10.1007/978-3-319-69155-8_2
Autor:
Wallace Mann, Per Enge, Nainesh Agarwal, John N. Tsitsiklis, Andrew Chou, Julien Basch, Piyush Bharti, Stefano Casadei, Neesha Hathi, Jesse Stone, Paul Eric Beckmann, Scott Bloebaum, Benjamin Van Roy, Wungkum Fong, Anant Sahai
Publikováno v:
GPS Solutions. 6:149-160
The proliferation of mobile devices and the emergence of wireless location-based services has generated consumer demand for availability of GPS in urban and indoor environments. This demand calls for enhanced GPS algorithms that accommodate high degr
Autor:
Nainesh Agarwal, Nikitas J. Dimopoulos
Publikováno v:
2010 53rd IEEE International Midwest Symposium on Circuits and Systems.
Finite State Machine with Datapath (FSMD) partitioning is an effective technique for isolating circuit components. The isolated components can be clock gated or power gated to achieve dramatic power savings. FSMD partitioning typically relies on a hi
Autor:
Nikitas J. Dimopoulos, Nainesh Agarwal
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783642031373
SAMOS
SAMOS
We propose a technique to efficiently partition a FSMD (Finite State Machine with Datapath) using a simulated annealing approach. The FSMD is split into two or more simpler communicating processors. These separate processors can then be clock gated o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b3cf194f198dcab1998d8a5cdba1d4b
https://doi.org/10.1007/978-3-642-03138-0_12
https://doi.org/10.1007/978-3-642-03138-0_12
Autor:
Nainesh Agarwal, Nikitas J. Dimopoulos
Publikováno v:
ISVLSI
It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partitioning technique which considers both the controller and the datapath togeth
Autor:
Nainesh Agarwal, Nikitas J. Dimopoulos
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540736226
SAMOS
SAMOS
In this paper, we use the CoDeL hardware design platform to analyze the potential and performance impact of power gating individual registers. For each register, we examine the percentage of clock cycles for which they can be powered off, and the los
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a4be9c4c73370c70cdcbf71d6c4635b5
https://doi.org/10.1007/978-3-540-73625-7_31
https://doi.org/10.1007/978-3-540-73625-7_31
Autor:
Nikitas J. Dimopoulos, Nainesh Agarwal
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540364108
SAMOS
SAMOS
We present a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. Our language, called CoDeL, allows hardware description at the algorithm level, and thus dramatically reduces design time. We
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5157f6f5f13165bda974b9a2d7432859
https://doi.org/10.1007/11796435_10
https://doi.org/10.1007/11796435_10
Autor:
Nainesh Agarwal, Nikitas J. Dimopoulos
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540223771
SAMOS
SAMOS
The focus of this work is on techniques that promise to reduce the message delivery latency in message passing environments, incuding clusters of workstations or SMPs. We are introducing Network Processing extensions, and present a preliminary implem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ee56b8be011244c460b7df4a38af1df5
https://doi.org/10.1007/978-3-540-27776-7_35
https://doi.org/10.1007/978-3-540-27776-7_35