Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Naga Durga Prasad Avirneni"'
Publikováno v:
PeerJ Computer Science, Vol 2, p e79 (2016)
Timing Speculation (TS) is a widely known method for realizing better-than-worst-case systems. Aggressive clocking, realizable by TS, enable systems to operate beyond specified safe frequency limits to effectively exploit the data dependent circuit d
Externí odkaz:
https://doaj.org/article/318cc2c4f6404170ab026c39392c9a7a
Autor:
Naga Durga Prasad Avirneni
Advances in the fabrication technology have been a major driving force in the unprecedented increase in computing capabilities over the last several decades. Despite huge reductions in the switching energy of the transistors, two major issues have em
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d7e59aefe131fc0373a60e17633757f3
https://doi.org/10.31274/etd-180810-2225
https://doi.org/10.31274/etd-180810-2225
Publikováno v:
IEEE Transactions on Computers. 63:1408-1420
Recent events have indicated that attackers are banking on side-channel attacks, such as differential power analysis (DPA) and correlation power analysis (CPA), to exploit information leaks from physical devices. Random dynamic voltage frequency scal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1d8bd85d5b3ea783f1bfa3bdc7ae2acc
https://doi.org/10.1109/tc.2013.9
https://doi.org/10.1109/tc.2013.9
Publikováno v:
PeerJ Computer Science, Vol 2, p e79 (2016)
Timing Speculation (TS) is a widely known method for realizing better-than-worst-case systems. Aggressive clocking, realizable by TS, enable systems to operate beyond specified safe frequency limits to effectively exploit the data dependent circuit d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9f6272dca12130b7516c5bbcaa41b629
https://doi.org/10.7287/peerj.preprints.1412v2
https://doi.org/10.7287/peerj.preprints.1412v2
Publikováno v:
IEEE Transactions on Computers. 61:488-501
The threat of soft error induced system failure in computing systems has become more prominent, as we adopt ultradeep submicron process technologies. In this paper, we propose two efficient soft error mitigation schemes, namely, Soft Error Mitigation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::abd24694df56b608e3ce81b2c90ee761
https://doi.org/10.1109/tc.2011.31
https://doi.org/10.1109/tc.2011.31
Publikováno v:
DSN
The threat of soft error induced system failure in high performance computing systems has become more prominent, as we adopt ultra-deep submicron process technologies. In this paper, we propose two techniques, namely Soft Error Mitigation (SEM) and S
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3ec1c265f34a881e83fe8e125f75e584
https://doi.org/10.1109/dsn.2009.5270340
https://doi.org/10.1109/dsn.2009.5270340
Publikováno v:
DSN
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, this has special implications since the operating frequency of the entire
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::18532baa004d5dee97253e053ba3f117
https://doi.org/10.1109/dsn.2007.90
https://doi.org/10.1109/dsn.2007.90
Publikováno v:
ACM Transactions on Architecture & Code Optimization; Jan2019, Vol. 15 Issue 4, p1-27, 27p
Publikováno v:
IEEE Transactions on Computers; Jan2017, Vol. 66 Issue 1, p178-182, 5p
Publikováno v:
IEEE Transactions on Computers; Mar2016, Vol. 65 Issue 3, p979-991, 13p