Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Nafiul Alam Siddique"'
Publikováno v:
The Journal of Supercomputing. 74:665-695
Cache has long been used to minimize the latency of main memory accesses by storing frequently used data near the processor. Processor performance depends on the underlying cache performance. Therefore, significant research has been done to identify
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0ceb53b029012cfc313ee3ed18ad68a9
https://doi.org/10.1007/s11227-017-2144-1
https://doi.org/10.1007/s11227-017-2144-1
Publikováno v:
MEMSYS
This paper proposes a novel cache architecture that uses spare cache blocks to work as back up blocks in a set associative cache, which can operate reliably at voltages well below the manufacturing induced operating voltage (Vccmin). We detect errors
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::29ff98b57c6c753da340b9a69cfee5cc
https://doi.org/10.1145/3132402.3132441
https://doi.org/10.1145/3132402.3132441
Publikováno v:
MEMSYS
In this paper, we present an on-chip memory store called "Local Memory Store (LMStr)"which can be used with a regular cache hierarchy or solely as a redesigned scratchpad memory (SPM). The LMStr is a shared special kind of a SPM among the cores in a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b3da72d182c0d06004027121eb501715
https://doi.org/10.1145/3132402.3132440
https://doi.org/10.1145/3132402.3132440
Autor:
Nafiul Alam Siddique, Strahinja Trecakov, Jaime C. Acosta, Casey Tran, Hameed Badawy, Satyajayant Misra
Publikováno v:
MASS
As technology improves in size and the number of smart devices increases, security in personal devices undoubtedly becomes an important aspect of today's life. However, the complexity in hardware and software systems expose vulnerabilities in securit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ec99fcdb45bc4ee51245503c05fec942
https://doi.org/10.1109/mass.2017.100
https://doi.org/10.1109/mass.2017.100
Publikováno v:
SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI
We present an on-chip memory store called “Local Memory Store” (LMStr). The LMStr can be used with a regular cache hierarchy or solely as a redesigned scratchpad memory (SPM). The LMStr is a shared special kind of SPM among the cores in a multico
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::41e13384c502e79fb5d50bfc786903a8
https://doi.org/10.1109/uic-atc.2017.8397630
https://doi.org/10.1109/uic-atc.2017.8397630
Publikováno v:
SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI
This paper proposes a novel cache architecture that uses spare cache blocks to work as back up blocks in a set associative cache, which can operate reliably at voltages well below the manufacturing induced operating voltage (V ccmin ). We detect erro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9487ec9c38dfa45bf03f780cf73de79b
https://doi.org/10.1109/uic-atc.2017.8397619
https://doi.org/10.1109/uic-atc.2017.8397619
Publikováno v:
SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI
Computer architects have been utilizing cache hierarchies to improve performance by minimizing latency of main memory accesses via caching frequently used data closer to the core. The majority of prior research focuses on measuring cache hit rates an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::01a75ac4c05d182c68198e9ca7a45b10
https://doi.org/10.1109/uic-atc.2017.8397629
https://doi.org/10.1109/uic-atc.2017.8397629
Publikováno v:
2017 IEEE International Conference on Imaging, Vision & Pattern Recognition (icIVPR).
In this paper, we present an intelligent system where agents can co-ordinate creative tasks through machine learning and cooperation. For machine learning, we used commonly used pattern recognition algorithm - Principal Component Analysis (PCA). Base
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a6321d3efb862e6aa334e4004d32364e
https://doi.org/10.1109/icivpr.2017.7890884
https://doi.org/10.1109/icivpr.2017.7890884
Publikováno v:
2016 International Conference on Computational Science and Computational Intelligence (CSCI).
Cache hierarchies have long been utilized to minimize the latency of main memory accesses by caching frequently used data closer to the processor. Significant research has been done to identify the most crucial metrics of cache performance. Though th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0049eeb6085a6649ae38de62e5e07f86
https://doi.org/10.1109/csci.2016.0110
https://doi.org/10.1109/csci.2016.0110
Publikováno v:
IPCCC
In this paper, we present a hardware controlled on-chip memory called Local Memory Store (LMStr) that can be used either solely as a scratchpad or as a combination of scratchpad and cache, storing any variable specified by the programmer or extracted
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c01cb75dbd7bb690175514d7e4e15d53
https://doi.org/10.1109/pccc.2016.7820661
https://doi.org/10.1109/pccc.2016.7820661