Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Nael Mizanur Rahman"'
Autor:
Nael Mizanur Rahman, Saibal Mukhopadhyay, Venkata Chaitanya Krishna Chekuri, Arvind Singh, Edward Lee
Publikováno v:
IEEE Transactions on Industrial Electronics. 69:3120-3130
Publikováno v:
2023 IEEE International Solid- State Circuits Conference (ISSCC).
Autor:
Jinwoo Kim, Nael Mizanur Rahman, Hakki Mert Torun, Majid Ahadi Dolatsara, Venkata Chaitanya Krishna Chekuri, Sung Kyu Lim, Madhavan Swaminathan, Saibal Mukhopadhyay
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:2148-2157
In this article, we present an effective methodology for co-design, co-analysis and the system-level optimization of chiplet/interposer power delivery network (PDN) in 2.5D IC designs. In our methodology, we first generate a commercial-grade heteroge
Autor:
Shida Zhang, Nael Mizanur Rahman, Venkata Chaitanya Krishna Chekuri, Carlos Tokunaga, Saibal Mukhopadhyay
Publikováno v:
ACM/IEEE International Symposium on Low Power Electronics and Design.
Autor:
Jamin Seo, Mandovi Mukherjee, Nael Mizanur Rahman, Jianming Tong, Coleman DeLude, Tushar Krishna, Justin Romberg, Saibal Mukhopadhyay
Publikováno v:
2022 IEEE/MTT-S International Microwave Symposium - IMS 2022.
Autor:
Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Kallol Roy, Sung Kyu Lim, Hakki Mert Torun, Hyoukjun Kwon, Nihar Dasari, Madhavan Swaminathan, Tushar Krishna, Eric Qin, Heechun Park, Gauthaman Murali, Saibal Mukhopadhyay, Jinwoo Kim, Minah Lee, Arvind Singh
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28:2424-2437
A new trend in system-on-chip (SoC) design is chiplet-based IP reuse using 2.5-D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This approach expand
Autor:
Dae Hyun Kim, Nael Mizanur Rahman, Xueyuan She, Venkata Chaitanya Krishna Chekuri, Saibal Mukhopadhyay
Publikováno v:
IEEE Solid-State Circuits Letters. 3:278-281
A processing-in-memory (PIM)-based accelerator is presented in 65-nm CMOS for on-chip learning in spiking neural network using timing-based stochastic spike-timing-dependent plasticity (STDP). The design uses mixed-signal processing in the 8T-SRAM ar
Autor:
Saurabh Dash, Saibal Mukhopadhyay, Nael Mizanur Rahman, Jongseok Woo, Dae Hyun Kim, Yun Long, Mandovi Mukherjee
Publikováno v:
IEEE Solid-State Circuits Letters. 3:450-453
An all-digital flexible precision in-memory accelerator for vector matrix multiplication (VMM) is demonstrated in 65 nm CMOS. The design supports flexible precision, floating point, and complex numbers enabling in-memory radio-frequency machine learn
Autor:
Hakki Mert Torun, Sung Kyu Lim, Saibal Mukhopadhyay, Jinwoo Kim, Majid Ahadi Dolatsara, Madhavan Swaminathan, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman
Publikováno v:
ICCD
The optimal selection of an interposer substrate is important in 2.5D systems, because its physical, material and electrical characteristics govern the overall system performance, reliability and cost. Several materials have been proposed that offer
Autor:
Edward Lee, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Saibal Mukhopadhyay, Arvind Singh
Publikováno v:
IRPS
This paper analyzes degradation of transient performance of on-chip voltage regulators, namely, a digital low dropout regulator (DLDO) and an integrated inductive voltage regulator (IVR), due to negative-bias-temperature-instability (NBTI) induced ag