Zobrazeno 1 - 7
of 7
pro vyhledávání: '"N. S. S. Reddy"'
Publikováno v:
International Journal of VLSI and Signal Processing. 4:14-24
Publikováno v:
Learning and Analytics in Intelligent Systems ISBN: 9783030243173
The collective fabrication of electronic devices let alone the rise within their speed has given an incredible success in the field of small and nano natural philosophy. Linear scaling of the device dimensions to a quasi-nano meter level permits the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::726259d8fa94978c40b72a39b4853c83
https://doi.org/10.1007/978-3-030-24318-0_34
https://doi.org/10.1007/978-3-030-24318-0_34
Publikováno v:
Learning and Analytics in Intelligent Systems ISBN: 9783030243173
In the recent times most of the advanced circuits designing projects are using reversible logic since it is helping to decrease the configuration dependent warmth scattering. This allows vitality free calculation, high range of circuit density and be
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a694abc4c939dce8cda2bc99bf96c94f
https://doi.org/10.1007/978-3-030-24318-0_33
https://doi.org/10.1007/978-3-030-24318-0_33
Publikováno v:
International Journal of Engineering Research and.
Publikováno v:
2017 International Conference on Communication and Signal Processing (ICCSP).
The paper presents low power and area efficient LMS (Least Mean Square) adaptive filter. Least Mean Squares algorithm used in many DSP applications to process the signal and designed for generating filter coefficients based on the processed signal. T
Publikováno v:
2016 International Conference on Communication and Signal Processing (ICCSP).
Now a days, low power Very Large Scale Integration (VLSI) circuit plays an important role in designing efficient energy saving electronic systems for high speed performance. In VLSI, low power dissipation is the main criterion in many electronic devi
Publikováno v:
2016 International Conference on Communication and Signal Processing (ICCSP).
This present paper, a 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 180 nm technology. The proposed results are compared with the previous existing designs in