Zobrazeno 1 - 10
of 55
pro vyhledávání: '"N. Jossart"'
Autor:
E. Raymenants, D. Wan, S. Couet, Y. Canvel, A. Thiam, D. Tsvetanova, L. Souriau, I. Asselberghs, R. Carpenter, N. Jossart, M. Manfrini, A. Vaysset, O. Bultynck, S. Van Beek, M. Heyns, D.E. Nikonov, I.A. Young, S. Ghosh, L. Vila, K. Garello, S. Pizzini, V.D. Nguyen, I.P. Radu
Publikováno v:
2021 IEEE International Electron Devices Meeting (IEDM)
2021 IEEE International Electron Devices Meeting (IEDM), Dec 2021, San Francisco, United States. pp.32.3.1-32.3.4, ⟨10.1109/IEDM19574.2021.9720689⟩
2021 IEEE International Electron Devices Meeting (IEDM), Dec 2021, San Francisco, United States. pp.32.3.1-32.3.4, ⟨10.1109/IEDM19574.2021.9720689⟩
International audience
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6514f3ee5a0a8a8fecbd4457301eaff6
https://hal.science/hal-03768245
https://hal.science/hal-03768245
Autor:
S. H. Sharifi, Simon Van Beek, Shreya Kundu, Sebastien Couet, N. Jossart, Gouri Sankar Kar, Siddharth Rao
Publikováno v:
Electronics, Vol 10, Iss 2384, p 2384 (2021)
Electronics
Volume 10
Issue 19
Electronics
Volume 10
Issue 19
Spin-transfer torque magnetoresistive random access memory (STT-MRAM) technology is considered to be the most promising nonvolatile memory (NVM) solution for high-speed and low power applications. Dual MgO-based composite free layers (FL) have driven
Autor:
D. Crotti, F. Yasin, W. Kim, N. Jossart, Sebastien Couet, S. Van Beek, Ludovic Goux, Shreya Kundu, Gouri Sankar Kar, Stefan Cosemans, S. H. Sharifi, R. Carpenter, Siddharth Rao, M. Perumkunnil, Barry O'Sullivan, Laurent Souriau
Publikováno v:
2021 IEEE International Memory Workshop (IMW).
We present a detailed study of the impact of damage minimizing patterning schemes on the electrical performance of perpendicular STT-MRAM devices at array level, compatible with 22 nm CMOS technology node. By employing a novel patterning scheme invol
Autor:
S. H. Sharifi, Stefan Cosemans, R. Carpenter, D. Crotti, Shreya Kundu, N. Jossart, Sebastien Couet, Barry O'Sullivan, Farukh Yasin, Siddharth Rao, Woojin Kim, Simon Van Beek, Gouri Sankar Kar
Publikováno v:
IRPS
To enable high density STT-MRAM, process-induced damage needs to be minimized. High temperature anneals and patterning can degrade performance and reliability. By employing a novel patterning scheme, involving physical ion beam etch, etchback and oxi
Autor:
Harold Dekkers, M. Mao, Siddharth Rao, D. Crotti, Gouri Sankar Kar, Adrian Chasin, Sofie Mertens, Andrea Fantini, Manoj Nag, S. Houshmand Sharifi, N. Jossart
Publikováno v:
2020 IEEE International Memory Workshop (IMW).
For the first time at our knowledge, we demonstrate a sub-µm indium-gallium-zinc oxide (a-IGZO) (vertical) Schottky diodes on a 300mm platform. We demonstrate that the choice of a suitable Al2O3-based encapsulation layer is critical in order to achi
Autor:
H. Hody, S. H. Sharifi, Jianhong Wu, Siddharth Rao, R. Carpenter, F. Yasin, Kevin Garello, N. Jossart, Johan Swerts, K. K. V. Sethu, Laurent Souriau, M. Pak, Woojin Kim, Sebastien Couet, Gouri Sankar Kar, D. Crotti, Arnaud Furnemont
Publikováno v:
2019 Symposium on VLSI Circuits
2019 Symposium on VLSI Circuits, Jun 2019, Kyoto, France. pp.T194-T195, ⟨10.23919/VLSIC.2019.8778100⟩
VLSI Circuits
2019 Symposium on VLSI Circuits, Jun 2019, Kyoto, France. pp.T194-T195, ⟨10.23919/VLSIC.2019.8778100⟩
VLSI Circuits
We propose a field-free switching SOT-MRAM concept that is integration friendly and allows for separate optimization of the field component and SOT/MTJ stack properties. We demonstrate it on a 300 mm wafer, using CMOS-compatible processes, and we sho
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::43779dc1a8bc27d577fdc1bdd8f0b51e
https://hal.archives-ouvertes.fr/hal-03239895/file/VLSI_SOT-MRAM_FieldFree_vff.pdf
https://hal.archives-ouvertes.fr/hal-03239895/file/VLSI_SOT-MRAM_FieldFree_vff.pdf
Autor:
Tom Raymaekers, G. Van den bosch, N. Jossart, M. Pak, M. Baryshnikova, Bernardette Kunert, J. Stiers, Patrick Ong, Lieve Teugels, Leqi Zhang, Erik Rosseel, Antonio Arreghini, S. Vadakupudhu Palayam, S. Ramesh, Arnaud Furnemont
Publikováno v:
2019 IEEE 11th International Memory Workshop (IMW).
We demonstrate for the first time epitaxially grown InGaAs macaroni channel down to 15 nm thickness for 3-D NAND with a low temperature ( OFF w.r.t. full channel is demonstrated, while retaining a similar ION of full channel InGaAs and same memory pe
Autor:
E. Vecchio, Tom Raymaekers, Erik Rosseel, C.-L. Tan, N. Jossart, Leqi Zhang, G. Van den bosch, M. Pak, Laurent Breuil, S. S. V-Palayam, Romain Delhougne, Arnaud Furnemont, Antonio Arreghini, Laura Nyns, Andriy Hikavyy
Publikováno v:
2018 IEEE Symposium on VLSI Technology.
We are demonstrating for the first time epi-based monocrystalline silicon macaroni channel 3-D NAND devices. The highly controllable channel replacement process sequence leads to > 95% yield, with excellent uniformity and reproducibility, proving its
Autor:
Manuel Baumgartner, N. Jossart, Johan Swerts, S. Van Beek, D. Crotti, Eva Grimaldi, Pietro Gambardella, Gouri Sankar Kar, Shreya Kundu, F. Yasin, Laurent Souriau, Kevin Garello, Sebastien Couet, Diana Tsvetanova, Enlong Liu, A. Fumemont, W. Kim, Kristof Croes, Siddharth Rao
Publikováno v:
VLSI Circuits
2018 IEEE Symposium on VLSI Circuits
2018 IEEE Symposium on VLSI Circuits, Jun 2018, Honolulu, United States. pp.81-82, ⟨10.1109/VLSIC.2018.8502269⟩
Proceedings of the 2018 IEEE Symposium on VLSI Circuits
2018 IEEE Symposium on VLSI Circuits
2018 IEEE Symposium on VLSI Circuits, Jun 2018, Honolulu, United States. pp.81-82, ⟨10.1109/VLSIC.2018.8502269⟩
Proceedings of the 2018 IEEE Symposium on VLSI Circuits
We demonstrate for the first time full-scale integration of top-pinned perpendicular MTJ on 300 mm wafer using CMOS-compatible processes for spin-orbit torque (SOT)-MRAM architectures. We show that 62 nm devices with a W-based SOT underlayer have ver
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a75051dd8003aabdeb9c8add87fb9d6c
Autor:
S. Van Elshocht, Enlong Liu, J. Swerts, S. Van Beek, Sofie Mertens, N. Jossart, Kevin Garello, Thibaut Devolder, W. Kim, Arnaud Furnemont, Siddharth Rao, D. Crotti, Laurent Souriau, Sushil Sakhare, Gouri Sankar Kar, Barry O'Sullivan, F. Yasin, Sebastien Couet, Shreya Kundu
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
For the first time, we report on 400°C compatible top-pinned perpendicular magnetic tunnel junction (MTJ) stacks with dual MgO free layer for STT-MRAM applications. Using a texture-inducing parallel-coupling barrier layer (TICPB), we enforce the pin