Zobrazeno 1 - 10
of 70
pro vyhledávání: '"N. Jangkrajarng"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27:791-802
Layout parasitics can significantly affect the performance of analog integrated circuits (ICs). In this paper, a systematic method of optimizing an existing analog layout considering parasitics is presented for technology migration and performance re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ffd43478c9bdb5386805e3cd944de4ad
https://doi.org/10.1109/tcad.2008.917594
https://doi.org/10.1109/tcad.2008.917594
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25:945-960
The strong impact of layout intricacies on analog-circuit performance poses great challenges to analog layout automation. Recently, template-based methods have been shown to be effective in reuse-centric layout automation for CMOS analog blocks such
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6aeb1a3b98184bcfc3ade6780bdd9eb6
https://doi.org/10.1109/tcad.2005.855982
https://doi.org/10.1109/tcad.2005.855982
Publikováno v:
ICCD
A 1024-bit, 1/2-rate fully parallel low-density parity-check (LDPC) code decoder has been designed and implemented using a three-dimensional (3D) 0.18 mum fully depleted silicon-on-insulator (FDSOI) CMOS technology based on wafer bonding. The 3D-IC d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c49ac3b5faab0db525c16bb5536017d1
https://doi.org/10.1109/iccd.2007.4601900
https://doi.org/10.1109/iccd.2007.4601900
Publikováno v:
ASP-DAC
A 1024-bit, 1/2 -rate fully parallel low density parity check (LDPC) code decoder has been designed and implemented using a 3D 0.18/spl mu/m fully depleted silicon-on-insulator (FDSOI) CMOS technology based on wafer bonding. The taped-out 3D decoder
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9e1cb0146900ec1dd7ed49ae0026092b
https://doi.org/10.1109/aspdac.2006.1594652
https://doi.org/10.1109/aspdac.2006.1594652
Publikováno v:
ICCAD
Parasitic effects are extremely significant for the performance of analog and RF integrated circuits. Although layout retargeting for technology migration or specification update is able to preserve designers' intent, the associated layout parasitics
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::15df66a90f30e1452a32f7f76ab53d4a
https://doi.org/10.1145/1233501.1233570
https://doi.org/10.1145/1233501.1233570
Publikováno v:
VLSI Design
This paper presents a technique for automatic active device layout generation and insertion incorporated in a layout retargeting tool-suite for analog integrated circuits. While the use of a graph-based symbolic template in the retargeting tool maint
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cf06b3987ff865df6348e5771ebd8004
https://doi.org/10.1109/icvd.2005.60
https://doi.org/10.1109/icvd.2005.60
Publikováno v:
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::141603efd17a50ca2546292cb7d6c5b9
https://doi.org/10.1109/aspdac.2004.1337608
https://doi.org/10.1109/aspdac.2004.1337608
Publikováno v:
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::401af6998d4372738b8f9449661a33f4
https://doi.org/10.1109/aspdac.2004.1337607
https://doi.org/10.1109/aspdac.2004.1337607
Publikováno v:
DAC
Aggressive design cycles in the semiconductor industry demand a design-reuse principle for analog circuits. The strong impact of layout intricacies on analog circuit performance necessitates design reuse with special focus on layout aspects. This pap
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5ec49afde37a8ce3cfa3ce3e829227d3
https://doi.org/10.1145/996566.996609
https://doi.org/10.1145/996566.996609
Publikováno v:
ISCAS (4)
This paper presents an automatic analog layout resizing tool that can generate a new layout incorporating the target technology process and the target transistor sizes. The tool automatically preserves the analog layout integrity by extracting layout
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d47f17c8aeb14ee1524bc7e3c3e152ae
https://doi.org/10.1109/iscas.2003.1206224
https://doi.org/10.1109/iscas.2003.1206224