Zobrazeno 1 - 5
of 5
pro vyhledávání: '"N. I. Maluf"'
Autor:
B. P. van Drieënhuizen, N. I. Maluf
Publikováno v:
Microelectromechanical Systems (MEMS).
This paper presents a single crystal silicon accelerometer with high dynamic range fabricated in a CMOS compatible, low cost technology. This technology uses a combination of Silicon Fusion Bonding (SFB) and Deep Reactive Ion Etching (DRIE). which al
Autor:
Harvey I-Heng Liu, N. M. Johnson, N. I. Maluf, David K. Biegelsen, Roger Fabian W. Pease, Fernando Ponce
Publikováno v:
Optical Properties of Low Dimensional Silicon Structures ISBN: 9789401049276
Understanding the electronic structures of silicon (Si) nanostructures is essential for exploring their potential applications in opto-electronics. Well behaved and ordered Si nanostrctures are desirable for facilitating the characterization process
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::558ec869d3f2e4ac1254b13b96e63fbd
https://doi.org/10.1007/978-94-011-2092-0_3
https://doi.org/10.1007/978-94-011-2092-0_3
Autor:
David K. Biegelsen, Fernando Ponce, Noble M. Johnson, Harvey I-Heng Liu, N. I. Maluf, Roger Fabian W. Pease
Publikováno v:
MRS Proceedings. 283
Fabricating well controlled nanostructures and obtaining precise structural, electrical, and optical information from them are essential for understanding die intrinsic properties of silicon (Si) nanostructures, which in turn is important for explori
Publikováno v:
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures. 8:568
Trenches in a layer of SiO2 on Si, with feature sizes down to 0.125 μm have been filled with tungsten (W) using selective chemical vapor deposition (CVD). The trenches were formed in a fashion similar to contact vias by reactive ion etching the SiO2
Autor:
J. P. McVittie, Stephen Y. Chou, N. I. Maluf, Roger Fabian W. Pease, S. W. J. Kuan, David R. Allee
Publikováno v:
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures. 7:1497
Formation of vertical‐walled, high‐aspect‐ratio, narrow trenches in silicon is often required in submicron VLSI semiconductor processing. Present trench etching processes suffer from undercutting of the mask and sloped or bulged sidewalls; and