A Lambert-Function Charge-Based Methodology for Extracting Electrical Parameters of Nanoscale FinFETs

Autor: Charalabos A. Dimitriadis, A. Tsormpatzoglou, Gerard Ghibaudo, N. Fasarakis, D. H. Tassis, K. A. Papathanasiou

Publikováno v: IEEE Transactions on Electron Devices. 59:3299-3305

We developed a new Y-based methodology for extracting the electrical parameters in modern nanoscale double-gate and triple-gate FinFET devices. Using the drain-current equation in the linear region, which involves the Lambert W -function of the charg

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::83563c1ee36255a933cf48a0692a1594
https://doi.org/10.1109/ted.2012.2222647

Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs

Autor: Ilias Pappas, N. Fasarakis, Gerard Ghibaudo, Charalabos A. Dimitriadis, Matthias Bucher, A. Tsormpatzoglou, K. A. Papathanasiou, D. H. Tassis

Publikováno v: IEEE Transactions on Electron Devices. 59:1891-1898

An analytical compact drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field-effect transistors (finFETs) is presented, taking into account quantum-mechanical and short-channel effects such as threshold-voltage

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9f35706ccce8f9117a76a72919cc7236
https://doi.org/10.1109/ted.2012.2195318

Hot carrier degradation modeling of short-channel n-FinFETs

Autor: Ioannis Messaris, Gerard Ghibaudo, T.A. Karatsori, C.A. Dimitriadis, N. Fasarakis, A. Tsormpatzoglou

Publikováno v: 2015 DRC Proceedings
2015 73rd Annual Device Research Conference (DRC)
2015 73rd Annual Device Research Conference (DRC), Jun 2015, Columbus, United States. pp.183-184, ⟨10.1109/DRC.2015.7175617⟩

session poster; International audience; Figure 1(a) shows the degradation of the transfer characteristics of a typical FinFET with W fin = 10 nm, measured at V d = 0.03 V after HC stress at V stress = 1.8 V for different stress times. The degradation

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4d6558a8f4c1cfddacb814fa0007a580
https://hal.archives-ouvertes.fr/hal-02049708

An analytical model for the CMOS inverter

Autor: Maria Ntogramatzi, Spiridon Nikolaidis, N. Fasarakis, Panagiotis Chaourani, Sotirios K. Goudos, Ioannis Messaris

Publikováno v: PATMOS

A new analytical model for the CMOS inverter is introduced. This model results by solving analytically the differential equation which describes the inverter operation. It uses new simplified transistor current expressions which are developed taking

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::fb1bced46e20194863e6186ea0358faf
https://doi.org/10.1109/patmos.2014.6951894

Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

Autor: T.A. Karatsori, Olivier Faynot, Christoforos G. Theodorou, Charalabos A. Dimitriadis, N. Fasarakis, Gerard Ghibaudo, D. H. Tassis, Francois Andrieu

Publikováno v: IEEE Transactions on Electron Devices
IEEE Transactions on Electron Devices, 2014, 61 (4), pp.969-975. ⟨10.1109/TED.2014.2306015⟩
IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2014, 61 (4), pp.969-975. ⟨10.1109/TED.2014.2306015⟩

International audience; Simple analytical models for the front and back gate threshold voltages and ideality factors with back gate control of lightly doped short channel fully depleted silicon-on-insulator ultrathin body and buried oxide thickness M

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::eae7ef1d70ee21be04ad1b420aa9d4be
https://hal.science/hal-01947604