Zobrazeno 1 - 10
of 30
pro vyhledávání: '"N. Emonet"'
Autor:
A. Beverina, V. Huard, N. Emonet, R. Velard, J.-P. Carrere, Sébastien Petitdidier, I. Guilmeau, F. Guyader
Publikováno v:
Solid State Phenomena. 92:235-238
Publikováno v:
Journal of Photochemistry and Photobiology B: Biology. 40:84-90
The sensitivity of human dermal fibroblasts to UVA radiation has been linked to a decrease in intracellular glutathione (GSH) levels. GSH (γ-glutamyl-cysteinyl-glycine) is a radical scavenger and a cofactor for protective enzymes such as selenium-de
Autor:
J. Bienacel, Kathy Barla, D. Roy, M. Bidaud, L. Vishnubhotla, N. Emonet, D. Barge, I. Pouilloux
Publikováno v:
Materials Science in Semiconductor Processing. 7:181-183
Plasma nitridation of thermally grown oxide films has proven to be an excellent gate dielectric in meeting the electrical requirements of the 65 nm node. As the 65 nm device performance is very sensitive to both physical thickness and nitrogen dose o
Autor:
H. Del-Puppo, F. Lalanne, Bruce Boeck, N. Emonet, Audrey Berthelot, Christian Caillat, Vincent Huard, S. Barnola
Publikováno v:
2006 European Solid-State Device Research Conference.
For the first time, we report a complete evaluation of a TiN/ZrO 2/TiN stacked capacitor suitable for 45 nm embedded DRAM (eDRAM). Indeed, this study, done on a real integration (65 nm 3D stacked capacitor flow), shows that zirconium oxide, deposited
Autor:
S. Jullian, D. Delille, Yves Morand, R. Pantel, T. Farjot, V. Carron, C. Laviron, Florian Cacho, Benoit Froment, D. Bensahel, Abdelkader Souifi, D. Aime, N. Emonet, Aomar Halimaoui, Marc Juhel, R. Molins, Francois Wacquant, S. Descombes
Publikováno v:
Scopus-Elsevier
Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2005. EuroSimE 2005.
Electron Devices Meeting, 2004. IEDM Technical Digest
Electron Devices Meeting, 2004. IEDM Technical Digest, 2004, pp.87-90, ⟨10.1109/IEDM.2004.1419073⟩
Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2005. EuroSimE 2005.
Electron Devices Meeting, 2004. IEDM Technical Digest
Electron Devices Meeting, 2004. IEDM Technical Digest, 2004, pp.87-90, ⟨10.1109/IEDM.2004.1419073⟩
International audience; A wide workfunction (/spl Phi//sub m/) tuning range from 4.29eV to 4.99eV using total silicidation of doped polysilicon gate with nickel is presented. As, B and P but also N, Ge, Sb, In and co-implants, have been investigated
Autor:
Nathalie Revil, N. Emonet, P. Llinares, R. Difrenza, M. Denais, Roland Pantel, M. Woo, Vincent Huard, Kathy Barla, J. C. Vildeuil, H. Brut, C. Parthasarthy, M. Bidaud, P. Stolk, Franck Arnaud, David Roy, F. Guyader, K. Rochereau, L. Vishnubotla, D. Barge, Nicolas Planes, Sylvie Bruyere, B. Tavel
Publikováno v:
IEEE International Electron Devices Meeting 2003.
This work shows the benefits of using plasma nitrided gate oxide which supports the gate leakage requirements for 65 nm platform development. Electrical data shows gate leakage to be reduced by half a decade compared to conventional NO processing wit
Autor:
P.O. Sassoulas, Francois Wacquant, J. Todeschini, M. Woo, M. Charpin, Y. Laplanche, N. Revil, J.C. Oberlin, Roland Pantel, B. Hinschberger, O. Belmont, D. Neira, P. Stolk, Franck Arnaud, M. Broekaart, Frederic Boeuf, I. Guilmeau, D. Ceccarelli, Francois Leverd, N. Emonet, Damien Lenoble, Bertrand Borot, G. Imbert, N. Bicais, S. Delmedico, A. Sicard, Nicolas Planes, J. Farkas, Christophe Regnier, V. Vachellerie, J. Uginet, Chittoor Parthasarathy, E. Denis, V. DeJonghe, Pierre Morin, T. Devoivre, H. Brut, R. Palla, Laurent Pain, P. Vannier, F. Salvetti, A. Beverina, C. Perrot
Publikováno v:
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
This work highlights a 65 nm CMOS technology platform for low power and general-purpose applications. A 6-T SRAM cell size of 0.69 /spl mu/m/sup 2/ with a 45 nm gate length is demonstrated. Electrical data of functional SRAM bit-cell is presented at
Autor:
M. Denais, J. Todeschini, R.A. Bianchi, Damien Lenoble, Laurent Pain, Y. Laplanche, Franck Arnaud, H. Brut, M. Broekaart, Nicolas Planes, V. Vachellerie, M. Woo, A. Beverina, Pierre Morin, R. Difrenza, Bertrand Borot, C. Perrot, H. Leninger, Francois Wacquant, D. Barge, David Roy, F. Salvetti, D. Ceccarelli, N. Emonet, V. DeJonghe, P. Stolk, B. Tavel, B. Duriez, L. Vishnobulta, I. Guilmeau, Y. Loquet, Frederic Boeuf, T. Devoivre, N. Bicais, J.P. Reynard, M. Jurdit, K. Rochereau, R. Palla, F. Judong, M. Bidaud, P. Vannier, D. Reber
Publikováno v:
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 /spl mu/m/sup 2/ 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution. Fully wor
Autor:
N. Emonet, S. Jullian, Frederic Boeuf, C. Perrot, F. Payet, J. M. Hartmann, C. Laviron, Y. Campidelli, Pierre Morin, Francois Leverd, N. Villani, V. Carron, O. Kermarrec, N. Casanova, Thomas Skotnicki, D. Bensahel, Franck Arnaud
Publikováno v:
Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials.
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