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Publikováno v:
NANO 2020-20th IEEE International Conference on Nanotechnology, Proceedings: Proceedings
NANO 2020-20th IEEE International Conference on Nanotechnology, Proceedings
NANO 2020-20th IEEE International Conference on Nanotechnology, Proceedings
As CMOS scaling is reaching its limits, high power density and leakage, low reliability, and increasing IC production costs are prompting for developing new materials, devices, architectures, and computation paradigms. Additionally, temperature varia
Publikováno v:
NANOARCH
2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
Designing and implementing artificial systems that can be interfaced with the human brain or that can provide computational ability akin to brain's processing information efficient style is crucial for understanding human brain fundamental operating
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Publikováno v:
ISCAS 2020: IEEE International Symposium On Circuits & Systems
ISCAS
ISCAS
Designing and implementing artificial neuromorphic systems, which can provide biocompatible interfacing, or the human brain akin ability to efficiently process information, is paramount to the understanding of the human brain complex functionality. E
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Publikováno v:
ISCAS
Hysteretic behavior has been experimentally observed in graphene-based structures and has a major influence on graphene surface potential and gate field modulation ability. Thus, a graphene electronic transport modelling methodology, which incorporat
Publikováno v:
2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO).
Graphene, due to its wealth of remarkable electronic properties, emerged as a potent post-Si forerunner for nanoelectronics. To enable the exploration and evaluation of potential graphene-based circuit designs, we propose a fast and accurate Verilog-
Publikováno v:
ISCAS
As CMOS feature size approaches atomic dimensions, unjustifiable static power, reliability, and economic implications are exacerbating, prompting for research and development on new materials, devices, and/or computation paradigms. Within this contex
Autor:
N. Cucu Laurenciu, Sorin Cotofana
Publikováno v:
SoCC
In this paper we introduce and evaluate Haar based codec assisted medium and long range data transport structures, e.g., bus segments, Network on Chip interconnects, able to deal with technology scaling related phenomena (e.g., increased susceptibili
Autor:
Sorin Cotofana, N. Cucu Laurenciu
Publikováno v:
SMACD
A fast, yet accurate nanoscale IC energy estimation is a design-time desideratum for area-delay-power-reliability optimized circuits and architectures. This paper introduces an IC energy estimation approach, which instead of sequentially propagating
Autor:
N. Cucu Laurenciu, Sorin Cotofana
Publikováno v:
Journal of Parallel and Distributed Computing. 74:2512-2520
Accurate age modeling, and fast, yet robust reliability sign-off emerged as mandatory constraints in Integrated Circuits (ICs) design for advanced process technology nodes. In this paper we introduce a novel method to assess and predict the circuit r