Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Myriam Assous"'
Autor:
Myriam Assous, Benoit Charbonnier, Stephane Malhouitre, Pascal Vivet, Jean Charbonnier, Denis Dutoit, Yvain Thonnart, Ayse K. Coskun, Pierre Tissier, Aditya Narayan, Damien Saint-Patrice, Christian Bernard, David Coriat, Stephane Bernabe, Cesar Fuguet
Publikováno v:
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2020, Grenoble, France. pp.1456-1461, ⟨10.23919/DATE48585.2020.9116214⟩
DATE 2020-Design, Automation & Test in Europe Conference & Exhibition
DATE 2020-Design, Automation & Test in Europe Conference & Exhibition, Mar 2020, Grenoble, France. pp.1456-1461, ⟨10.23919/DATE48585.2020.9116214⟩
DATE
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2020, Grenoble, France. pp.1456-1461, ⟨10.23919/DATE48585.2020.9116214⟩
DATE 2020-Design, Automation & Test in Europe Conference & Exhibition
DATE 2020-Design, Automation & Test in Europe Conference & Exhibition, Mar 2020, Grenoble, France. pp.1456-1461, ⟨10.23919/DATE48585.2020.9116214⟩
DATE
International audience; Silicon photonics technology is now gaining maturity with increasing levels of design complexity from devicesto large photonic integrated circuits. Close integration of control electronics with 3D assembly of photonics and CMO
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6a9a59fe45846bc31b16019d3b533b5e
https://hal-cea.archives-ouvertes.fr/cea-03471376
https://hal-cea.archives-ouvertes.fr/cea-03471376
Autor:
Myriam Assous, S. Simic, A. Plihon, C. Hartler, Jean Charbonnier, Jörg Siegert, Werner Grogger, Stefan Mitsche, Franz Schrank, Stephane Moreau, E. Chery
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 18:313-320
Die-to-wafer interconnections such as copper pillars play a vital role in order to enable 3-D integration. This interconnection type allows increasing the density of interconnects but the occurrence of defects, especially intermetallic compounds (IMC
Autor:
Jean Charbonnier, Pierre Tissier, R. Coquand, Gabriel Pares, Thierry Mourier, Sophie Verrun, R. Franiatte, Stephane Minoret, F. Allain, Mehmet Bicer, Myriam Assous, C. Ribiere
Publikováno v:
69th Electronic Components and Technology Conference
69th Electronic Components and Technology Conference, May 2019, Las Vegas, United States. pp.1622-1628, ⟨10.1109/ECTC.2019.00249⟩
69th Electronic Components and Technology Conference, May 2019, Las Vegas, United States. pp.1622-1628, ⟨10.1109/ECTC.2019.00249⟩
International audience; Micro pillars and micro bumps interconnections are considered as mature technology for 3-D integration and chip stacking. However, in the framework of high-energy particles detection as ATLAS Large Hadron Collider new tracker
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::112192c5ae8aee2a47a8c2ab0b5895a9
https://hal.archives-ouvertes.fr/hal-02475226
https://hal.archives-ouvertes.fr/hal-02475226
Autor:
Myriam Assous, Stephane Moreau, Jean Charbonnier, Jörg Siegert, Maxime Argoud, N. David, C. Hartler, Nacima Allouti, Ewald Wachmann, A. Plihon, C. Brunet-Manquat
Publikováno v:
2017 IEEE 19th Electronics Packaging Technology Conference (EPTC).
As electronic power systems follow the general trend of miniaturization and functional density [1], this study targets reliable and low cost 3D heterogeneous integration technology using Through Silicon Vias (TSV) and Wafer Level Packaging (WLP) for
Autor:
Myriam Assous, C. Brunet Manquat, T. Hilt, A. Plihon, C. Hartler, Thierry Mourier, H. Gruber, Jennifer Guillaume, Jean Charbonnier, J. P. Bally, Franz Schrank, A. Hassaine, R. Franiatte, K. Pressel, Jörg Siegert
Publikováno v:
2016 6th Electronic System-Integration Technology Conference (ESTC).
Electronic power systems follow the general trend of miniaturization and functional density. 3D technologies provide an interesting response if adapted to power specifications. In the framework of the ENIAC JU funded project Enhanced Power Pilot Line
Autor:
Kei Murayama, Robert Cuchet, Gilles Simon, Mitsuhiro Aizawa, Masahiro Sunohara, H. Feldis, Jean Charbonnier, Myriam Assous, Jean-Philippe Bally, Mitsutoshi Higashi, Ken Miyairi
Publikováno v:
International Symposium on Microelectronics. 2012:000984-000990
Silicon interposers with TSVs appear to open new possibilities thanks to high wiring density interconnections and improved electrical performances given by shorter interconnections from die to die and also from die to substrate. Silicon interposers a
Autor:
Myriam Assous, Mitsutoshi Higashi, Jean-Philippe Bally, Kenichi Mori, Ken Miyairi, Mitsuhiro Aizawa, Jean Charbonnier, Masahiro Sunohara, Gilles Simon, Koji Hara, Kei Murayama
Publikováno v:
2013 IEEE 63rd Electronic Components and Technology Conference.
In order to achieve high speed transmission and large volume data processing, large size silicon-interposer has been required. Warpage caused by the CTE mismatch between a large silicon-interposer and an organic substrate is the most significant prob
Autor:
Nathalie Bernard-Henriques, Jean Charbonnier, Rachid Hida, H. Feldis, Mitsutoshi Higashi, Nicole Bouzaida, Ken Miyairi, Masahiro Sunohara, Robert Cuchet, Jean-Philippe Bally, Myriam Assous, Thierry Mourier, Gilles Simon
Publikováno v:
2012 4th Electronic System-Integration Technology Conference.
As standard organic substrate packages and wire bonding are reaching their limits in term of wiring density and integration capacity, silicon interposer approach combined with 3D integration technologies opens new possibilities in advanced packaging.
Autor:
Patrick Leduc, Sophie Verrun, Laurent Bally, Marc Zussy, David Bouchu, Thomas Signamarcheix, Maxime Rousseau, Alexis Farcy, Lea Di Cioccio, Antonio Roman, Lionel Cadix, Nicolas Sillon, Myriam Assous
Publikováno v:
3DIC
Copper-filled Through-Si Vias (TSV) with diameters from 2 µm to 5 µm have been integrated in a die-to-wafer stack combining direct bonding and a planarization technique. TSVs were processed on chip backside after oxide bonding and substrate thinnin
Autor:
Laurent Clavelier, Lea Di Cioccio, Myriam Assous, Jerome Dechamp, Thomas Signamarcheix, Patrick Leduc, Rachid Taibi, Laurent Vandroux, Laurent Bally, Marc Zussy, Sophie Verrun, Francois de Crecy, Laurent-Luc Chapelon, D. Bouchu, Pierric Gueguen
Publikováno v:
3DIC
An innovative die to wafer stacking is proposed for 3D devices. Known good dices are bonded on a processed wafer thanks to direct bonding. Oxide layers or patterned oxide/copper layers are used as the bonding medium. After a first thinning, a low str