Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Myo Ei Pa Pa"'
Autor:
He Tong Kang, Chee Heng Fong, Ser Choong Chong, Zhonghai Wang, Myo Ei Pa Pa, Tai Chong Chai, Soon Wee Ho
Publikováno v:
2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013).
In this paper, a different type of through mold interconnects, known as Via-in-Mold (ViM) was developed for embedded wafer level package (EMWLP) to enable 3D stacking application. Via in Mold (ViM) interconnects are blind vias laser drilled into the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7c22f4ed6edc84ab5a3ccd87e8396a11
https://doi.org/10.1109/eptc.2013.6745845
https://doi.org/10.1109/eptc.2013.6745845
Autor:
Soon Wee Ho, Fernandez Moses Daniel, Wen-Sheng Lee, Pinjala Damaruganath, Myo Ei Pa Pa, Ser Choong Chong, Hyoung Joon Kim, Gao Shan
Publikováno v:
2011 IEEE 13th Electronics Packaging Technology Conference.
In this paper, a Via in Mold (ViM) interconnects were developed for embedded wafer level package (EMWLP) to enable 3D application. ViM interconnects are essentially plated blind vias drilled into the mold compound substrate. The two key processes req
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::03b3219e9dd4305e1d54a6ddbcafe6f2
https://doi.org/10.1109/eptc.2011.6184457
https://doi.org/10.1109/eptc.2011.6184457
Publikováno v:
2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
In an RF front-end module, the reduction of the antenna size is a challenge since it is dependent on the frequency of operation. In this paper, a method of antenna miniaturization is introduced, by employing a novel meander CPWG feed structure as wel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::11b2aea20041566eef10dd928cc7bca7
https://doi.org/10.1109/ectc.2011.5898688
https://doi.org/10.1109/ectc.2011.5898688
Autor:
Ling Xie, Won Kyoung Choi, C.S. Premachandran, A. Khairyanto, J.H. Lau, M. Chew, Kelvin Wei Sheng Chen, Myo Ei Pa Pa
Publikováno v:
2008 58th Electronic Components and Technology Conference.
Stacking of wafers with low chip-yield and non uniform chips size is developed for MEMS and 3D packaging applications. Stacking of MEMS and ASIC wafers one over other is difficult due to difference in chip yield and chip size. A cap wafer which is us
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2e53519320eb06a613f3afc968c7dfd
https://doi.org/10.1109/ectc.2008.4549988
https://doi.org/10.1109/ectc.2008.4549988
Publikováno v:
2011 IEEE 61st Electronic Components & Technology Conference (ECTC); 2011, p1354-1362, 9p
Autor:
Premachandran, C.S., Lau, J., Ling Xie, Khairyanto, A., Chen, K., Myo Ei Pa Pa, Chew, M., Won Kyoung Choi
Publikováno v:
2008 58th Electronic Components & Technology Conference; 2008, p314-318, 5p