FPGA-assisted Design Space Exploration of Parameterized AI Accelerators: A Quickloop Approach

Autor: Inayat, Kashif, Muslim, Fahad Bin, Mahmood, Tayyeb, Chung, Jaeyong

Publikováno v: In Journal of Systems Architecture October 2024 155

Implementation of Symbol Timing Recovery for Estimation of Clock Skew

Autor: Hashmi, S. M. Usman, Hussain, Muntazir, Muslim, Fahad Bin, Inayat, Kashif, Hwang, Seong Oun

Publikováno v: International Journal of Internet Technology and Secured Transactions (2020): https://www.inderscience.com/info/ingeneral/forthcoming.php?jcode=ijitst

Time synchronization in any distributed network can be achieved by using application layer protocols for time correction. Time synchronization method proposed in this article uses symbol timing recovery at the physical layer to correct application la

Externí odkaz: http://arxiv.org/abs/2006.14413

Power-Intent Systolic Array Using Modified Parallel Multiplier for Machine Learning Acceleration.

Autor: Inayat, Kashif¹ (AUTHOR), Muslim, Fahad Bin² (AUTHOR), Iqbal, Javed³ (AUTHOR) javed@ueas.edu.pk, Hassnain Mohsan, Syed Agha⁴ (AUTHOR), Alkahtani, Hend Khalid⁵ (AUTHOR), Mostafa, Samih M.⁶ (AUTHOR)

Publikováno v: Sensors (14248220). May2023, Vol. 23 Issue 9, p4297. 19p.

LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow

Autor: Qamar, Affaq ^*, Muslim, Fahad Bin, Iqbal, Javed, Lavagno, Luciano

Publikováno v: In Microprocessors and Microsystems May 2017 50:26-38

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