Zobrazeno 1 - 10
of 92
pro vyhledávání: '"Murugesan, Mariappan"'
Autor:
Toshiaki Shirasaka, Tadashi Okuda, Tomoaki Shibata, Satoshi Yoneda, Daisaku Matsukawa, Murugesan Mariappan, Mitsumasa Koyanagi, Takafumi Fukushima
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Autor:
Murugesan Mariappan, Shizu Fukuzumi, Tomoaki Shibata, Hiroyuki Hashimoto, JiChel Bea, Mitsumasa Koyanagi, Takafumi Fukushima
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Autor:
Takafumi Fukushima, Shinichi Sakuyama, Masatomo Takahashi, Hiroyuki Hashimoto, Jichoel Bea, Theodorus Marcello, Hisashi Kino, Tetsu Tanaka, Mitsumasa Koyanagi, Murugesan Mariappan
Publikováno v:
2021 IEEE International 3D Systems Integration Conference (3DIC).
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
° A physical vapor deposition (PVD) formed WNi thinfilm over M1 (metal level 1) after its revealing in the via-last through-Si-via (TSV) process has been investigated for its ability in protecting the M1 metal during electroless (EL) plating of barr
Autor:
Aizawa, Ryo, Shiina, Urara, Nampo, Jinta, Sawa, Masahiro, Ohno, Akinobu, Murugesan, Mariappan, Fukushima, Takafumi
Publikováno v:
ECS Meeting Abstracts; 2024, Vol. MA2024 Issue 2, p1956-1956, 1p
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
Si TEG chips containing Au-Sn micro-bumps (μ- bump) with various sizes (varying from 3 to 20 μm) and pitch values (between 6 μm and 30 μm) were fabricated, and the flip-chip bonded chips were characterized for micro-structure and electrical resis
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
The electroless (EL) Ni layer conformally formed inside the high aspect ratio (AR, >10) through-Si-via (TSV) has been investigated for its role as seed layer in bottom-up Cu electroplating. From the electro-chemical adsorption monitoring data it was
Akademický článek
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Autor:
Tetsu Tanaka, Rui Liang, Takafumi Fukushima, Murugesan Mariappan, Hisashi Kino, Sungho Lee, Kousei Kumahara, Yuki Miwa
Publikováno v:
3DIC
Through-silicon vias (TSVs) is one of the key technologies for 3D integration. To solve the issues induced by the high-temperature process for TSV liner formation in the multichip-to-wafer (MCtW) process, we applied the low-temperature SiO 2 depositi
Publikováno v:
3DIC
An advanced Directed-Self-Assembly (DSA) assisted vertical nano-scale interconnection formation has been attempted inside deep Si trench structures for ultra-high-density 3D storage memory application. Based on Flory-Huggins theory, nano-cylindrical