Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Murari Mani"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26:1790-1802
Variability in process parameters leads to a significant parametric yield loss of high-performance ICs due to the large spread in leakage-power consumption and speed of chips. In this paper, we propose an algorithm for total power minimization under
Publikováno v:
ISQED
In this paper, we present an efficient algorithm for large-scale leakage optimization under sign-off timing constraints using the technique of multiple voltage threshold (multi-Vt) assignment. Several practical considerations are addressed, such as t
Publikováno v:
2010 IEEE Dallas Circuits and Systems Workshop.
In many digital designs, multi-stage tapered buffers are needed to drive large capacitive loads. These buffers contribute a significant percentage of overall power. In this paper, we propose two novel tunable buffer designs that enable power reductio
Autor:
Murari Mani, Michael Orshansky
Publikováno v:
Closing the Power Gap Between ASIC & Custom ISBN: 9780387257631
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20df97603f4781089e4f527db0f0dc5f
https://doi.org/10.1007/978-0-387-68953-1_12
https://doi.org/10.1007/978-0-387-68953-1_12
Publikováno v:
ACM Great Lakes Symposium on VLSI
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interior-point solution method. The new solution method is capable of solving
Publikováno v:
DAC
The gain-based technology mapping paradigm has been successfully employed for finding minimum delay and minimum area mappings. However, existing gain-based technology mappers fail to find circuits with minimal leakage power. In this paper, we introdu
Publikováno v:
ICCAD
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable parameters. The two levels of tuning operate within a single variabili
Publikováno v:
DAC
Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics are treated probabilistically. Power reduction is performed by simulta
Autor:
Michael Orshansky, Murari Mani
Publikováno v:
ICCD
In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nanometer regime. We present a statistical sizing approach that takes into ac