Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Munhyeon Kim"'
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 11, Pp 95-100 (2023)
In this paper, floating fin structured vertically stacked nanosheet gate-all-around (GAA) metal oxide semiconductor field-effect transistor (FNS) is proposed for low power logic device applications. To verify the electrical performance of the propose
Externí odkaz:
https://doaj.org/article/ff78f69c60d84f17a0807c2f3e742c11
Publikováno v:
IEEE Electron Device Letters. 44:1007-1010
Autor:
Seunghwan Song, Munhyeon Kim, Bosung Jeon, Donghyun Ryu, Sihyun Kim, Kitae Lee, Jong-Ho Lee, Jae-Joon Kim, Wonbo Shim, Daewoong Kwon, Byung-Gook Park
Publikováno v:
IEEE Electron Device Letters. 43:1657-1660
Publikováno v:
IEEE Transactions on Electron Devices. 69:2088-2093
Publikováno v:
IEEE Transactions on Electron Devices. 69:1048-1053
Publikováno v:
IEEE Transactions on Nanotechnology. 21:534-538
Publikováno v:
IEEE Electron Device Letters. 42:1607-1610
In this letter, we propose a double-gated ferroelectric-gate field-effect-transistor (DG-FeFET) for processing-in-memory (PIM) operations in a single device for the first time. The proposed device is highly compatible with a conventional fin field-ef
Autor:
Munhyeon Kim, Sihyun Kim, Kitae Lee, Hyun-Min Kim, Changha Kim, Dong-Oh Kim, Byung-Gook Park, Daewoong Kwon
Publikováno v:
2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).
Autor:
Sihyun Kim, So Youn Kim, Ryoongbin Lee, Donghyun Ryu, Junil Lee, Kitae Lee, Sangwan Kim, Jong-Ho Lee, Munhyeon Kim, Byung-Gook Park
Publikováno v:
IEEE Transactions on Electron Devices. 67:2648-2652
In this brief, several issues attributed to the channel-release process in vertically stacked-gate-all-around MOSFETs (GAAFETs) having various nanosheet (NS) widths were rigorously investigated. Because of the finite selectivity of SiGe (sacrificial
Publikováno v:
IEEE Transactions on Electron Devices. 67:1859-1863
In this article, structure optimization of high- ${k}$ interfacial layer (IL), deposited between the gate and the gate sidewall spacer, was performed in a 5-nm node nanosheet field-effect transistor (NSFET). High- ${k}$ IL can be formed during the hi