Výsledky vyhledávání - "Multiplus multiprocessor"

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A comparative analysis of cache memory architectures for the MULTIPLUS multiprocessor

Autor: Ageu Cavalcanti Pacheco, J.S. Aude, Alexandre Malheiros Meslin

Publikováno v: Microprocessing and Microprogramming. 35:555-562

This paper analyses some design alternatives for the MULTIPLUS cache memory subsystem architecture. MULTIPLUS is a high performance multiprocessor system under development at NCE/UFRJ. The analysis is carried out using a simulator which supports diff

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c2eb272ab96b9d2f0dd563e8f02f246d
https://doi.org/10.1016/0165-6074(92)90368-h

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NCESPARC+: an implementation of a SPARC architecture with hardware support to multithreading for the multiplus multiprocessor

Autor: Aude, Júlio Salek, Martins, F. R. S., Barbosa, M. A. S., João Junior, M., Young, M.T., Pinto, S. B.

Publikováno v: Repositório Institucional da UFRJ
Universidade Federal do Rio de Janeiro (UFRJ)
instacron:UFRJ

Submitted by Elaine Almeida (elaine.almeida@nce.ufrj.br) on 2017-08-15T15:21:24Z No. of bitstreams: 1 27_99_000611360.pdf: 1730780 bytes, checksum: 65c02298a15e0c90d5135feb67c8ffa0 (MD5) Made available in DSpace on 2017-08-15T15:21:24Z (GMT). No. of

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NCESPARC+: A Multithreaded SPARC Architecture for the Multiplus Multiprocessor

Autor: J. S. Aude, F. R. S. Martins, M. A. S. Barbosa, M. Joao Jr., M. T. Young, S. B. Pinto

Publikováno v: Anais do XI International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 1999).

NCESPARC+ is a SPARC V.8 architecture with hardware support to a variable number of thread contexts, which is under development for use within the framework of the Multiplus distributed shared-memory multiprocessor. It is expected to provide an effic

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0ba44e1b0931e34997b639e568f3ae74
https://doi.org/10.5753/sbac-pad.1999.19769

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A polynomial-time branching procedure for the multiprocessor scheduling problem

Autor: Corrêa, Ricardo Cordeiro, Ferreira, Afonso

Publikováno v: Repositório Institucional da UFRJ
Universidade Federal do Rio de Janeiro (UFRJ)
instacron:UFRJ

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Uma Avaliação do Impacto das Operações de E/S no Desempenho do Multiprocessador Multiplus

Autor: Oliveira, Sidney de Castro, Aude, Júlio Salek

Publikováno v: Repositório Institucional da UFRJ
Universidade Federal do Rio de Janeiro (UFRJ)
instacron:UFRJ

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https://doi.org/10.5753/sbac-pad.1992.22723

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Multiplus: a modular high-performance multiprocessor

Autor: Aude, Júlio Salek, Cruz, Adriano Joaquim Oliveira, Pacheco Junior, Ageu Cavalcanti, Bronstein, Gerson, Meslin, Alexandre Malheiros, Oliveira, Sidney de Castro, Figueira, Norival R., Azevedo, Rafael Peixoto, Azevedo, Gustavo Peixoto de

Publikováno v: Repositório Institucional da UFRJ
Universidade Federal do Rio de Janeiro (UFRJ)
instacron:UFRJ

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Avaliação de uma alternativa de implementação para um microprocessador SPARC

Autor: Silva, Gabriel Pereira da, Aude, Júlio Salek

Publikováno v: Repositório Institucional da UFRJ
Universidade Federal do Rio de Janeiro (UFRJ)
instacron:UFRJ

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O Subsistema de Memória de Massa do Multiprocessador MULTIPLUS

Autor: Oliveira, Sidney de Castro, Aude, Júlio Salek

Publikováno v: Repositório Institucional da UFRJ
Universidade Federal do Rio de Janeiro (UFRJ)
instacron:UFRJ

Submitted by Elaine Almeida (elaine.almeida@nce.ufrj.br) on 2017-03-17T11:27:51Z No. of bitstreams: 1 34_90_000040400.pdf: 1274005 bytes, checksum: bd57d92691c80e4cfb26f946b98c1c0c (MD5) Made available in DSpace on 2017-03-17T11:27:51Z (GMT). No. of

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::465b28cb1106138c2310d28dd0338b76
https://doi.org/10.5753/sbac-pad.1990.23125

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Conference

The MULTIPLUS/MULPLIX parallel processing environment.

Autor: Aude, J.S., Meslin, A.M., Santos, C.M.P., Bronstein, G., Cordeiro, L.F.M., Barros, M.O., Joao, M., Oliveira, S.C.

Publikováno v: Proceedings Second International Symposium on Parallel Architectures, Algorithms & Networks (I-SPAN'96); 1996, p50-56, 7p

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