Zobrazeno 1 - 10
of 71
pro vyhledávání: '"Multiplier accumulator"'
Akademický článek
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Publikováno v:
2021 3rd Novel Intelligent and Leading Emerging Sciences Conference (NILES).
This paper discusses the implementation of a Multiplier Accumulator (MAC) design using memristor and crossbar architecture. MAC consists of an array of memristors alongside transistors making a cell that works as a switch (i.e., turned ON or OFF). Wh
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:560-568
The unique ability of dual-mode logic (DML) to self-adapt to computational needs by providing high speed and/or low energy consumption is demonstrated for the first time by silicon measurements in 28-nm fully depleted silicon on insulator. At the gat
Autor:
M. Gnanasekaran, J. Balamurugan
Publikováno v:
Intelligent Computing in Engineering ISBN: 9789811527791
In recent growing of portable and multimedia devices, such as notebooks, and video phones, motivated the researchers to design low power VLSI circuits. Multiplier Accumulator Unit (MAC) is a major element of DSP. The speed of systems is based on the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::57702c647664fec46821a3e577416288
https://doi.org/10.1007/978-981-15-2780-7_38
https://doi.org/10.1007/978-981-15-2780-7_38
Autor:
G. Umamaheswara Reddy, K. Rajesh
Publikováno v:
2019 Third International Conference on Inventive Systems and Control (ICISC).
The design of Multiplier-Accumulator (MAC) unit can be implemented by using the Vedic multiplier along with the reversible logic gates. The designing of Vedic multiplier is designed by using the new sutra called “Urdhava Triyagbhayam”. The perfor
Publikováno v:
ISCAS
Artificial neural network (NN) circuits are proposed and analyzed from the viewpoints of flexibility and robustness based on memristive devices. The typical 3-layered fully-connected NN is a primitive unit of Deep Learning (DL) and plays a key role i
Autor:
K V Santhosh, S Nithin
Publikováno v:
International Journal of Students' Research in Technology & Management. 3:413-415
In this paper, a new multiplier design is proposed which reduces the number of partial products by 25%. This multiplier has been used with different adders available in literature to implement multiplier accumulator (MAC) unit and parameters such as
Autor:
M.Tech Student , Ssits, Rayachoty, Kadapa Dist., India., Professor, Ssits, Rayachoty, Kadapa Dist., India., S. Tabasum, M.P. Chennaiah
Publikováno v:
i-manager's Journal on Embedded Systems. 2:7-13
Autor:
Rajiv S. Mishra, P. A. Irfan Khan
Publikováno v:
Indian Journal of Science and Technology. 9
Background/Objectives: Power consumption is one of the important designsin many digital signal processing applications, the main building blocks of the processor is Multiplier-Accumulator (MAC) unit. Methods/Statistical Analysis: In the present work,
Akademický článek
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