Zobrazeno 1 - 10
of 245
pro vyhledávání: '"Muhannad S. Bakir"'
Autor:
Sreejith Kochupurackal Rajan, Bharath Ramakrishnan, Husam Alissa, Washington Kim, Christian Belady, Muhannad S Bakir
Publikováno v:
IEEE Access, Vol 10, Pp 59259-59269 (2022)
The stagnation of Dennard scaling along with the move towards heterogeneous 2.5D and 3D ICs is increasing the thermal design power (TDP) envelopes of general-purpose CPUs. With conventional cooling approaches such as air-cooling and cold plates, it i
Externí odkaz:
https://doaj.org/article/de8f10f5c0de4700aa5359b347744449
Autor:
Ankit Kaul, Yandong Luo, Xiaochen Peng, Madison Manley, Yuan-Chun Luo, Shimeng Yu, Muhannad S. Bakir
Publikováno v:
IEEE Transactions on Electron Devices. 70:485-492
Autor:
Ting Zheng, Muhannad S. Bakir
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 12:2002-2012
Autor:
Md Obaidul Hossen, Ankit Kaul, Eriko Nurvitadhi, Mondira Deb Pant, Ravi Gutala, Aravind Dasu, Muhannad S. Bakir
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 12:1824-1831
Autor:
Muhannad S. Bakir
Publikováno v:
2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT).
Publikováno v:
IEEE Photonics Technology Letters. 34:1023-1025
Publikováno v:
Embedded and Fan‐Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces. :261-287
Autor:
Ting Zheng, Muhannad S. Bakir, Sreejith Kochupurackal Rajan, Jonathan R. Brescia, Joe L. Gonzalez
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:2069-2076
This paper presents a novel die-level, rePlaceable INtegrated CHiplet (PINCH) assembly using a socketed platform. To enable the replaceability of this tightly-integrated system, the appropriate set of enabling technologies is required. To this end, t
Autor:
Muhannad S. Bakir, Ming-Jui Li
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:2242-2245
We propose a 3D heterogeneous integration technology called 3D Integrated Chiplet-Encapsulation (3D ICE). The proposed 3D ICE architecture encapsulates chiplets into a reconstituted tier using low-temperature (100 °C) ICP-PECVD SiO2 deposition. The
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:2061-2068
This paper presents a novel substrate-agnostic self-alignment technology with submicron alignment accuracy targeted for heterogeneous integrated systems. This self-alignment technology, referred to as PSAS-to-PSAS self-alignment, incorporates positiv