Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Muhammad Ali Shami"'
Publikováno v:
Mehran University Research Journal of Engineering and Technology, Vol 37, Iss 3, Pp 483-492 (2018)
This paper confers one of the three phases of tree multipliers, i.e. the Partial Product reduction phase. In this paper four types of hybrid tree multipliers are studied and proposed using parallel counters (full adders and half adders) for reduction
Externí odkaz:
https://doaj.org/article/927cd3e93b9743c78b7d1d18601d5c6c
Autor:
Atif Raza Jafri, Javaria Majid, Muhammad Ali Shami, Muhammad Ali Imran, Muhammad Najam-Ul-Islam
Publikováno v:
IEEE Access, Vol 5, Pp 13401-13408 (2017)
The inclusion of machine-type communication in the 5G technology has motivated the research community to explore new derivative waveforms of orthogonal frequency division multiplexing. Filter bank multicarrier, universal filtered multicarrier (UFMC),
Externí odkaz:
https://doaj.org/article/0281374456c843b8ae9470bc043b5c01
Publikováno v:
Mehran University Research Journal of Engineering and Technology, Vol 37, Iss 3, Pp 483-492 (2018)
This paper confers one of the three phases of tree multipliers, i.e. the Partial Product reduction phase. In this paper four types of hybrid tree multipliers are studied and proposed using parallel counters (full adders and half adders) for reduction
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::eab35f5ca9d06568cedf66b3de97cd45
https://doi.org/10.22581/muet1982.1803.04
https://doi.org/10.22581/muet1982.1803.04
Publikováno v:
Journal of Signal Processing Systems. 91:459-473
This paper presents results of using a Coarse Grain Reconfigurable Architecture called DRRA (Dynamically Reconfigurable Resource Array) for FFT implementations varying in order and degree of parallelism using radix-2 decimation in time (DIT). The DRR
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4d18a14c9134624c6deef73e6489f461
https://doi.org/10.1007/s11265-017-1326-7
https://doi.org/10.1007/s11265-017-1326-7
Publikováno v:
IEEE Access, Vol 5, Pp 13401-13408 (2017)
The inclusion of machine-type communication in the 5G technology has motivated the research community to explore new derivative waveforms of orthogonal frequency division multiplexing. Filter bank multicarrier, universal filtered multicarrier (UFMC),
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::192ecde7ea538f2867be8a46d3449ef4
https://ieeexplore.ieee.org/document/7987685/
https://ieeexplore.ieee.org/document/7987685/
Autor:
Guo Chen, Wei Ye, Muhammad Adeel Tajammul, Muhammad Ali Shami, Shuo Li, Nasim Farahini, Ahmed Hemani
Publikováno v:
ISCAS
This paper presents an industrial case study of using a Coarse Grain Reconfigurable Architecture (CGRA) for a multi-mode accelerator for two kernels: FFT for the LTE standard and the Correlation Pool for the UMTS standard to be executed in a mutually
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3fab26678d970b887dc0895b6ec0a7c2
https://doi.org/10.1109/iscas.2013.6572129
https://doi.org/10.1109/iscas.2013.6572129
Autor:
Ahmed Hemani, Muhammad Ali Shami
Publikováno v:
IPDPS Workshops
Faced with slowing performance and energy benefits of technology scaling, VLSI/Computer architectures have turned from parallel to massively parallel machines for personal and embedded applications in the form of multi and many core architectures. Ad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d7ff82b9921895a66655279bdd54cfe4
https://doi.org/10.1109/ipdpsw.2012.42
https://doi.org/10.1109/ipdpsw.2012.42
Autor:
Ahmed Hemani, Muhammad Ali Shami
Publikováno v:
ASAP
In this paper, we describe a versatile address generation scheme for distributed storage resources of a coarse grain Parallel Distributed Digital Signal Processing (PDDSP) reconfigurable architecture under development in our group. This scheme propos
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::136ccf4cd5633e0e3fb175a6207c8648
https://doi.org/10.1109/asap.2011.6043232
https://doi.org/10.1109/asap.2011.6043232
Publikováno v:
VLSI Design
A framework for efficiently capturing the rich micro architectural space of a substantial Matlab like library of DSP functions for a regular Coarse Grain Reconfigurable Architecture (CGRA) fabric is proposed. A subset of C has been proposed to model
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7079c81b15f58c174c1520c8c1d75ef1
https://doi.org/10.1109/vlsid.2011.54
https://doi.org/10.1109/vlsid.2011.54
Publikováno v:
VLSI Design
This paper presents a Network-on-Chip based distributed partitionable memory system for a Dynamic Reconfigurable Resource Array (DRRA). The main purpose of this design is to extend the Register File (RFile) interface with additional data handling cap
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::684ce5b71c61c5a3394e38e577a7f698
https://doi.org/10.1109/vlsid.2011.45
https://doi.org/10.1109/vlsid.2011.45