Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Muhamed F. Mudawar"'
Autor:
Muhamed F. Mudawar
Publikováno v:
IEEE Access, Vol 11, Pp 17891-17905 (2023)
The IEEE 754 standard does not distinguish between exact and inexact floating-point numbers. There is no bit or field in the binary encoding that indicates whether a floating-point number is exact or not. This is the case for binary and decimal float
Externí odkaz:
https://doaj.org/article/6e62979494fa4f9a8fdd1fb7994cbac9
Autor:
Mohammed Al-Asli, Muhammad E. S. Elrabaa, Ayman Hroub, Muhamed F. Mudawar, Ahmad Khayyat, Amran Al-Aghbari
Publikováno v:
IEEE Transactions on Parallel and Distributed Systems. 28:3033-3045
Simulation is the main tool for computer architects and parallel application developers for developing new architectures and parallel algorithms on many-core machines. Simulating a many-core architecture represent a challenge to software simulators e
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 14:1-25
Requiring no functional simulation, trace-driven simulation has the potential of achieving faster simulation speeds than execution-driven simulation of multicore architectures. An efficient, on-the-fly, high-fidelity trace generation method for multi
Publikováno v:
2018 5th International Conference on Electrical and Electronic Engineering (ICEEE).
In the past, ARM and Intel x86 computer processors were leaders in the different specialized areas with no competing interest. While Intel was building processors for the PCs and servers, ARM was concentrated on the handheld devices. Nowadays, with n
Publikováno v:
Arabian Journal for Science and Engineering. 36:785-794
A rapid growth in the storage capacity requirements at a computer center can lead to the installation of additional disk racks. The challenging task is not the installation, but to migrate old data to the new storage pools. A framework to parallelize
Publikováno v:
2005 International Conference on Information and Communication Technology.
Simultaneous multithreading (SMT) is becoming one of the major trends in the design of future generations of microarchitectures. Its key strength comes from its ability to exploit both thread-level and instruction-level parallelism; it uses hardware
Autor:
Muhamed F. Mudawar
Publikováno v:
WMPI
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for band-width. The size of the L1 data cache did not scale over the past decade. Instead, larger unified L2 and L3 caches were introduced. This c