Zobrazeno 1 - 10 of 81 pro vyhledávání: '"Moreto Planas, Miquel"'
1
Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices
Autor: Reggiani, Enrico, Pappalardo, Alessandro, Doblas Font, Max, Moreto Planas, Miquel, Olivieri, Mauro, Unsal, Osman Sabri, Cristal Kestelman, Adrián, Barcelona Supercomputing Center
Publikováno v: 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA).
Deep Neural Network (DNN) inference based on quantized narrow-precision integer data represents a promising research direction toward efficient deep learning computations on edge and mobile devices. On one side, recent progress of Quantization-Aware
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fde9d74760a558898fe6a065f9c9f778
https://doi.org/10.1109/hpca56546.2023.10071076
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2
DynAMO: Improving parallelism through dynamic placement of atomic memory operations
Autor: Soria Pardos, Víctor, Armejach Sanosa, Adrià, Mück, Tiago, Suárez Gracía, Dario, Joao, Jose A., Rico, Alejandro, Moreto Planas, Miquel
With increasing core counts in modern multi-core designs, the overhead of synchronization jeopardizes the scalability and efficiency of parallel applications. To mitigate these overheads, modern cache-coherent protocols offer support for Atomic Memor
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=od______3484::c8887afabdf6bff87332c29de5fb139b
https://hdl.handle.net/2117/390752
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3
Fast behavioural RTL simulation of 10B transistor SoC designs with Metro-Mpi
Autor: López Paradís, Guillem, Li, Brian, Armejach Sanosa, Adrià, Wallentowitz, Stefan, Moreto Planas, Miquel, Balkind, Jonathan
Chips with tens of billions of transistors have become today's norm. These designs are straining our electronic design automation tools throughout the design process, requiring ever more computational resources. In many tools, parallelisation has imp
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=od______3484::1fc5ca8611102f71fe9d6afb6efcbc02
https://hdl.handle.net/2117/390396
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4
Microarchitectural design-space exploration of an in-order RISC-V processor in a 22nm CMOS technology
Autor: Doblas Font, Max, Wright, Andrew, Sonmez, Nehir, Moreto Planas, Miquel|||0000-0002-9848-8758, Arvind
Publikováno v: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
The purpose of this paper is to explore the trade-offs between IPC and maximum clock frequency in an in-order processor design. This work evaluates the impact on the performance and frequency of different pipeline optimizations. We target ASIC implem
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::ba759a381663bf244a7ea2cddda2c8e0
https://hdl.handle.net/2117/356636
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5
Enabling hardware randomization across the cache hierarchy in Linux-Class processors
Autor: Doblas, Max, Kostalampros, Ioannis-Vatistas, Moreto Planas, Miquel, Hernández Luz, Carles
Publikováno v: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
The most promising secure-cache design approaches use cache-set randomization to index cache contents thus thwarting cache side-channel attacks. Unfortunately, existing randomization proposals cannot be sucessfully applied to processors’ cache hier
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::d36ae7cd81e2691b109919ba9db66bb9
http://hdl.handle.net/2117/190692
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6
Towards resilient EU HPC systems: A blueprint
Autor: Radojković, Petar, Marazakis, Manolis, Carpenter, Paul Matthew, Jeyapaul, Reiley, Gizopoulos, Dimitris, Schulz, Martin, Armejach Sanosa, Adrià, Ayguadé Parra, Eduard, Canal Corretger, Ramon, Moreto Planas, Miquel, Salami, Behzad, Unsal, Osman Sabri
Publikováno v: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
This document aims to spearhead a Europe-wide discussion on HPC system resilience and to help the European HPC community define best practices for resilience. We analyse a wide range of state-of-the-art resilience mechanisms and recommend the most ef
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::3e45e3309e35a2378d499558f1be92d3
http://hdl.handle.net/2117/330695
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7
Adaptive Power Shifting for Power-Constrained Heterogeneous Systems
Autor: Ortega Carrasco, Cristobal, Alvarez Martí, Lluc, Buyuktosunoglu, Alper, Bertran Monfort, Ramon, Rosedahl, Todd Jon, Bose, Pradip, Moreto Planas, Miquel|||0000-0002-9848-8758
Publikováno v: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
The number and heterogeneity of compute devices, even within a single compute node, has been steadily on the rise. Since all systems must operate under a power cap, the number of discrete devices that can run simultaneously at their highest frequency
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6c53f4ac1479ea7c223ecfdd50819666
https://doi.org/10.1109/tc.2022.3174545
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10
An optimized predication execution for SIMD extensions
Autor: Barredo Ferreira, Adrián, Cebrián González, Juan Manuel, Moreto Planas, Miquel, Casas Guix, Marc, Valero Cortés, Mateo
Publikováno v: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Vector processing is a widely used technique to improve performance and energy efficiency in modern processors. Most of them rely on predication to support divergence control. However, performance and energy consumption in predicated instructions are
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::34e19db8369507b89f7425e4a0fd314a
http://hdl.handle.net/2117/328836
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