Zobrazeno 1 - 10
of 33
pro vyhledávání: '"Moongon Jung"'
Autor:
Moongon Jung1 moongon@gatech.edu, Mitra, Joydeep2 joydeep@ece.utexas.edu, Pan, David Z.2 dpan@ece.utexas.edu, Sung Kyu Lim1 limsk@ece.gatech.edu
Publikováno v:
Communications of the ACM. Jan2014, Vol. 57 Issue 1, p107-115. 9p. 2 Black and White Photographs, 5 Diagrams, 6 Charts, 5 Graphs.
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:2109-2117
Low power is considered as the driving force for 3-D ICs, yet there have been few thorough design studies on how to reduce power in 3-D ICs. In this paper, we discuss computer-aided design techniques and design methodologies to reduce power consumpti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fabb521b9c0c96f39a72e03dce9da9f9
https://doi.org/10.1109/tvlsi.2017.2670508
https://doi.org/10.1109/tvlsi.2017.2670508
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 5:1393-1401
Low power is widely considered as a key benefit of 3-D integrated circuits (ICs), yet there have been few thorough design studies on how to maximize power benefits in 3-D ICs. In this paper, we present design methodologies to reduce power consumption
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::02f7fe982b0340683613d02be61798b4
https://doi.org/10.1109/tcpmt.2015.2470124
https://doi.org/10.1109/tcpmt.2015.2470124
Publikováno v:
IEEE Transactions on Electron Devices. 62:940-946
Dimensional scaling of interconnects at future technology generations presents major limitations to the improvement of the performances of integrated circuits. In this paper, we investigate the impact of highly scaled Cu/low- $\kappa $ interconnects
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e983e71bf15fce104b406ec3cddb75e5
https://doi.org/10.1109/ted.2015.2394407
https://doi.org/10.1109/ted.2015.2394407
Autor:
Taigon Song, Guanhao Shen, Ho Choi, Shreepad Panth, Dong Hyuk Woo, Young-Joon Lee, Moongon Jung, Ilya Khorosh, Gokul Kumar, Chang Liu, Mohammad M. Hossain, Michael B. Healy, Krit Athikulwongse, Sung Kyu Lim, Mohit Pathak, Minzhen Ren, Dean L. Lewis, Xin Zhao, Joungho Kim, Tzu-Wei Lin, Hsien-Hsin S. Lee, Gabriel H. Loh, Dae Hyun Kim
Publikováno v:
IEEE Transactions on Computers. 64:112-125
This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technol
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3381e1f4d4b71a283205e0b3f0214ab8
https://doi.org/10.1109/tc.2013.192
https://doi.org/10.1109/tc.2013.192
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32:1694-1707
In this paper, we propose a fast and accurate chip/package thermomechanical stress co-analysis tool for through-silicon-via (TSV)-based 3-D ICs. We use our tool for full-stack mechanical reliability as well as stress-aware timing analyses. First, we
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::845491e875a22dfec3f1fcf5f0596748
https://doi.org/10.1109/tcad.2013.2265372
https://doi.org/10.1109/tcad.2013.2265372
Publikováno v:
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).
In this paper we study the thermal impact of two high impact design/technology choices for 3D ICs, i.e., block folding and face-to-face bonding. A recent study shows that block folding and face-to-face improve wirelength, power, and performance, but
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5e60a89d52c1c19ab0fdb1fad8d051c5
https://doi.org/10.1109/iitc-mam.2015.7325593
https://doi.org/10.1109/iitc-mam.2015.7325593
Publikováno v:
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).
Despite many predictions that 3D IC is the solution for future low-power electronics, few studies describe how this can happen in real designs. In this paper, we investigate the practical design factors that affect the power consumption of 3D IC usin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::572ee006b9d3717c61dfebfd7a4b6856
https://doi.org/10.1109/iitc-mam.2015.7325594
https://doi.org/10.1109/iitc-mam.2015.7325594
Publikováno v:
DAC
Low power is widely considered as a key benefit of 3D ICs, yet there have been few thorough design studies on how to maximize power benefits in 3D ICs. In this paper, we present design methodologies to reduce power consumption in 3D ICs using a large
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fdfbb3406585e575f89917527d233539
https://doi.org/10.1145/2593069.2593167
https://doi.org/10.1145/2593069.2593167
Publikováno v:
IEEE International Interconnect Technology Conference.
We study the impact of material property variations in through-silicon-via (TSV) and its surrounding structures on the reliability and performance of 3D ICs. We focus on coefficient of thermal expansion (CTE) and Young's modulus variations for TSV, b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::29b0cc755f02c46148e2ad04f6cb70c8
https://doi.org/10.1109/iitc.2014.6831846
https://doi.org/10.1109/iitc.2014.6831846