Zobrazeno 1 - 10
of 66
pro vyhledávání: '"Moon Hyun Yoo"'
Publikováno v:
SID Symposium Digest of Technical Papers. 47:1162-1164
In this work, we investigate the influence of grain boundaries on the performance of polycrystalline silicon thin-film transistors (poly-Si TFTs) for high resolution active-matrix organic light-emitting diode (AMOLED) displays using Voronoi diagram.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ac434eeeba2122eb739fb2ab068830c3
https://doi.org/10.1002/sdtp.10856
https://doi.org/10.1002/sdtp.10856
Autor:
Mun-Soo Park, Dongsik Kong, Dae Hwan Kim, Sunwoong Choi, Jaehyeong Kim, Minkyung Bae, Dong Myong Kim, Moon-Hyun Yoo, Hyun Kwang Jeong, Keum-Dong Jung, Inseok Hur, Woojoon Kim, Yongsik Kim
Publikováno v:
SID Symposium Digest of Technical Papers. 43:1133-1136
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1106198234a81de239c467e3fc99bd42
https://doi.org/10.1002/j.2168-0159.2012.tb05993.x
https://doi.org/10.1002/j.2168-0159.2012.tb05993.x
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :3082-3085
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7be999a8956b3a8af7b83348dd9f0c1f
https://doi.org/10.1587/transfun.e92.a.3082
https://doi.org/10.1587/transfun.e92.a.3082
Publikováno v:
SPIE Proceedings.
Double-patterning technology (DPT) has been a primary lithography candidate of the sub-30nm technology node. The major concern of DPT is the critical dimension (CD) skew and overlay error between 1st and 2nd patterning, which cause the degradation of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eed13bc36922478d704af325784ea267
https://doi.org/10.1117/12.869978
https://doi.org/10.1117/12.869978
Autor:
Sooyoung Ahn, Younghoi Cheon, Jongeun Koo, Bo-Sun Hwang, Jong-bae Lee, Chanseok Hwang, Moon-Hyun Yoo
Publikováno v:
ISQED
With the increase in circuit frequency and supply voltage Scaling, a robust power network design is essential to ensure that the circuits on a chip operate reliably at the guaranteed level of performance. Traditionally the power network analysis has
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8685bf0747b24757689f529d07c5be31
https://doi.org/10.1109/isqed.2011.5770799
https://doi.org/10.1109/isqed.2011.5770799
Autor:
Gyu-Tae Kim, Sanghoon Lee, Chul-Hong Park, Ji-Young Lee, A-Young Je, Jeong-Hoon Lee, Soo-Han Choi, Moon-Hyun Yoo, James Word
Publikováno v:
SPIE Proceedings.
As the optical lithography advances into the sub-30nm technology node, the various candidates of lithography have been discussed. Double dipole lithography (DDL) has been a primary lithography candidate due to the advantages of a simpler process and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2bc99fa1d50336bfbdec9e0bf13fc0f8
https://doi.org/10.1117/12.864081
https://doi.org/10.1117/12.864081
Autor:
Yong-Hee Park, Yong-Un Jang, Gi-young Yang, Yohan Kim, Young-Kwan Park, Moon-Hyun Yoo, Jongwook Jeon, Chilhee Chung
Publikováno v:
2010 International Conference on Simulation of Semiconductor Processes and Devices.
A predictive MOSFET model is very critical for early circuit design in nanoscale CMOS technologies. In this work, we developed a new compact MOSFET model which can dramatically improve the predictability of BSIM4 for the major 3 process and 2 layout
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ae94e8e05a93317d831e96c156978e70
https://doi.org/10.1109/sispad.2010.5604545
https://doi.org/10.1109/sispad.2010.5604545
Autor:
Moon-Hyun Yoo, Keun-Ho Lee, Young-Kwan Park, Dae Sin Kim, Juyul Lee, Zhiliang Xia, Chilhee Chung
Publikováno v:
2010 International Conference on Simulation of Semiconductor Processes and Devices.
A comprehensive simulation to investigate the charge loss mechanisms in planar and raised STI NAND-type charge trapping flash (CTF) memories with careful calibrations is present. The tunneling and silicon nitride trap transport with Poole-Frenkel (PF
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bdc259b79cd36bfbc49aa3f68fa07c01
https://doi.org/10.1109/sispad.2010.5604520
https://doi.org/10.1109/sispad.2010.5604520
Autor:
Keun-Ho Lee, Tai-Kyung Kim, Moon-Hyun Yoo, Inkook Jang, Young-Kwan Park, Alexander Schmidt, Chilhee Chung
Publikováno v:
2010 International Conference on Simulation of Semiconductor Processes and Devices.
A compact process model of the thickness of amorphous layer generated by high dose ion implantation was developed. The model takes into account implantation temperature that has strong effect on the damage accumulation and amorphization dynamics. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::68f77a601fba7e101e9254afce9a725a
https://doi.org/10.1109/sispad.2010.5604529
https://doi.org/10.1109/sispad.2010.5604529
Publikováno v:
2nd Asia Symposium on Quality Electronic Design (ASQED).
Power consumption has become a key constraint in VLSI designs. Leakage current becomes a dominant part of the total power dissipation. In addition, with technology scaling into sub-50nm regime, one of the main design challenges in the presence of pro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ebed1100adf69aef637ff0999ed161e0
https://doi.org/10.1109/asqed.2010.5548246
https://doi.org/10.1109/asqed.2010.5548246