Výsledky vyhledávání - "Moon Han Park"

Effects of stress on solid-phase epitaxial regrowth and corner defect generation in As+-implanted, two-dimensional amorphized Si

Autor: Yu Gyun Shin, Jeong Yong Lee, H. K. Kang, Moon Han Park

Publikováno v: Journal of Crystal Growth. 231:107-114

The effect of stress induced by chemical vapor deposited SiO 2 films on the solid-phase epitaxial regrowth and the corner defect generation in As + -implanted, two-dimensional amorphized Si has been studied. A trench structure was used to form the tw

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3500c8692ef669a654ee41636aeb7815
https://doi.org/10.1016/s0022-0248(01)01506-8

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Effective reduction of threshold voltage variability and standby leakage using advanced co-implantation and laser anneal for low power applications

Autor: Ji Hye Yi, Hwa-Sung Rhee, Sun Me Lim, Moon Han Park, Hoi-sung Chung, Nae-In Lee, Yong Shik Kim, J.S. Yoon, Myung Sun Kim, Min Sun Kim, Ho Lee

Publikováno v: 2008 IEEE International Electron Devices Meeting.

We have successfully reduced threshold voltage variation by combination of co-implantation and laser spike anneal on 45 nm low power SoC platform with conventional poly-Si/SiON gate stack. Doping profiles of CMOSFET channel is modulated through co-im

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c1c1038447ec6deb8068ccc91be1ade5
https://doi.org/10.1109/iedm.2008.4796849

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Highly controllable cyclic selective epitaxial growth (CySEG) for 65nm CMOS technology and beyond

Autor: Nae-In Lee, Kwang-Pyuk Suh, Ho Lee Moon Han Park, Seung-Hwan Lee, Tetsuji Ueno, Ho-Kyu Kang, Hwa-Sung Rhee, Dong-Suk Shin

Publikováno v: IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

A new novel raised source/drain (RSD) process by using cyclic selective epitaxial growth (CySEG) has been firstly proposed to enhance device performance for 65nm CMOSFETs and beyond. CySEG is effective in reducing the gate poly depletion effect by el

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ebbb25957fc58a2977b01733b81b8cb2
https://doi.org/10.1109/iedm.2004.1419377

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Novel plasma enhanced atomic layer deposition technology for high-k capacitor with EOT of 8 Å on conventional metal electrode

Autor: Yong-Min Yoo, Dae-jin Kwon, Ho-Kyu Kang, Yong-kuk Jeong, Choon-Soo Lee, Jae-Hwan Ka, Duck-Hyung Lee, Moon-han Park, Hong-ki Kim, Dae-Youn Kim, Kwan-Young Yun, Kwang-Pyuk Suh, Seok-jun Won

Publikováno v: 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

We have developed a plasma enhanced atomic layer deposition(PEALD) technology for high-k dielectrics such as Al/sub 2/O/sub 3/,Ta/sub 2/O/sub 5/ and HfO/sub 2/. Film quality and throughput of PEALD are far superior to that of ALD which has been spotl

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::fb5d3c0a2be10885a3aebcc68a0899c3
https://doi.org/10.1109/vlsit.2003.1221067

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Ultimate solution for low thermal budget gate spacer and etch stopper to retard short channel effect in sub-90 nm devices

Autor: Joo-Won Lee, Myung-Hwan Oh, Ja-hum Ku, Kang-soo Chu, Nae-In Lee, Jong-Ho Yang, Ho-Kyu Kang, Jun-Ha Lee, Jae-Eun Park, Hee-Sung Kang, Kwang-Pyuk Suh, Moon-han Park

Publikováno v: 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

For the first time, by employing low thermal budget processes of ALD SiO/sub 2/ and ALD SiN as gate spacer and silicide blocking layer, the short channel effects of CMOSFETs are significantly suppressed. Using the ALD SiO/sub 2/ and ALD SiN processes

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::fa742533006859e5e221246ad493a9cd
https://doi.org/10.1109/vlsit.2003.1221083

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High quality high-k MIM capacitor by Ta/sub 2/O/sub 5//HfO/sub 2//Ta/sub 2/O/sub 5/ multi-layered dielectric and NH/sub 3/ plasma interface treatments for mixed-signal/RF applications

Autor: Weon-Hong Kim, Ho-Kyu Kang, Dae-jin Kwon, Moon-han Park, Seok-jun Won, Joo-Hyun Jeong, Min-Woo Song, Kwang-Pyuk Suh, Yong-kuk Jeong, Hansu Oh

Publikováno v: Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Novel high-k MIM capacitor technology for mixed-signal/RF applications has been successfully developed by introducing multilayered high-k dielectric(Ta/sub 2/O/sub 5//HfO/sub 2//Ta/sub 2/O/sub 5/) and NH/sub 3/ plasma electrode-dielectric interfaces

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::411ecb2dacf7f9178faf80c2b48ccf11
https://doi.org/10.1109/vlsit.2004.1345491

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Mass-productive ultra-low temperature ALD SiO/sub 2/ process promising for sub-90 nm memory and logic devices

Autor: Ja-hum Ku, Jae-Eun Park, Ho-Kyu Kang, Seung-Hwan Lee, Cheol-Ho Shin, Moon-han Park, Joo-Won Lee, Byoung-Chul Kim, Byoung-Ha Cho, Nae-In Lee, Jong-Ho Yang, Kang-soo Chu, Kwang-Pyuk Suh

Publikováno v: Digest. International Electron Devices Meeting.

For the first time, ultra-low temperature ALD SiO/sub 2/ is successfully developed and applied on W/WN/poly-Si stack gates as a dual spacer for the enhancement of data retention time. ALD SiO/sub 2/ deposition is performed at 75/spl deg/C using HCD a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5eab951fe0fb6b49dc00f22251498397
https://doi.org/10.1109/iedm.2002.1175819

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Void free and low stress shallow trench isolation technology using P-SOG for sub 0.1 μm device

Autor: Hyun-Duk Cho, Soo-jin Hong, Dong-ho Ahn, Moon-han Park, U-In Chung, K. Fujihara, Jin-Hwa Heo, Yong-chul Oh, Joo-Tae Moon

Publikováno v: 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Highly reliable void free shallow trench isolation (VF-STI) technology by employing polysilazane based inorganic spin-on-glass (P-SOG) is developed for sub-0.1 /spl mu/m devices. In order to overcome the difficulties from the gap-filling and accumula

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::508d71571f447b4b7dae6ae62c7e119d
https://doi.org/10.1109/vlsit.2002.1015422

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50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications

Publikováno v: Digest. International Electron Devices Meeting.

A 90 nm generation logic technology with Cu/low-k interconnects is reported. 50 nm transistors are employed using gate oxide 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 /spl mu/A/pm and 360 /spl mu/A/

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::03770676f50bf22edbea0b3fe37525b4
https://doi.org/10.1109/iedm.2002.1175781

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A novel simple shallow trench isolation (SSTI) technology using high selective CeO/sub 2/ slurry and liner SiN as a CMP stopper

Autor: Taek Kyu Park, Y.H. Kim, H.-K. Kang, Moon-han Park, Moonyong Lee, H.B. Shin, Han Sin Lee, K.W. Park, Jun-Ran Kim

Publikováno v: 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

A novel simple shallow trench isolation technology, SSTI, has been developed. SSTI consists of direct trench etching masked only with the photoresist, trench oxidation, liner SiN deposition, CVD oxide trench fill, densification, and high selectivity

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::493a41b81d42a14928ec0a4426e3992e
https://doi.org/10.1109/vlsit.1999.799392

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