Zobrazeno 1 - 10
of 48
pro vyhledávání: '"Monodeep Kar"'
Autor:
Jinwook Oh, Alyssa Herbert, Marcel Schaal, Zhibin Ren, Ching Zhou, Siyu Koswatta, Naigang Wang, Matthew Cohen, Vidhi Zalani, Howard M. Haynie, Matthew M. Ziegler, Sae Kyu Lee, Brian W. Curran, Monodeep Kar, Martin Lutz, Xin Zhang, Robert Casatuta, Vijayalakshmi Srinivasan, Nianzheng Cao, Sunil Shukla, Pong-Fei Lu, Leland Chang, Michael A. Guillorn, Bruce M. Fleischer, Michael R. Scheuermann, Joel Abraham Silberman, Kerstin Schelm, Vinay Velji Shah, Chia-Yu Chen, Kailash Gopalakrishnan, Swagath Venkataramani, Hung Tran, Mingu Kang, Wei Wang, Jungwook Choi, Scot H. Rider, Jinwook Jung, James J. Bonanno, Radhika Jain, Li Yulong, Xiao Sun, Silvia Melitta Mueller, Kyu-hyoun Kim, Ankur Agrawal
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:182-197
Reduced precision computation is a key enabling factor for energy-efficient acceleration of deep learning (DL) applications. This article presents a 7-nm four-core mixed-precision artificial intelligence (AI) chip that supports four compute precision
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2998556a11fb9c2dbdc4775ef363b4bb
https://doi.org/10.1109/jssc.2021.3120113
https://doi.org/10.1109/jssc.2021.3120113
Autor:
H. Ekin Sumbul, Monodeep Kar, Himanshu Kaul, Knag Phil, Amit Agarwal, Raghavan Kumar, Seongjong Kim, Gregory K. Chen, Steven K. Hsu, Mark A. Anders, Ram Krishnamurthy
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:1082-1092
A binary neural network (BNN) chip explores the limits of energy efficiency and computational density for an all-digital deep neural network (DNN) inference accelerator. The chip intersperses data storage and computation using computation near memory
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49532421a40cd1229c2471de5afbe4d0
https://doi.org/10.1109/jssc.2020.3038616
https://doi.org/10.1109/jssc.2020.3038616
Autor:
Arvind Singh, Venkata Chaitanya Krishna Chekuri, Saibal Mukhopadhyay, Anto Kavungal Davis, Monodeep Kar, Madhavan Swaminathan, Mohamed Lamine Faycal Bellaredj
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 67:3083-3087
Integration of high frequency buck regulators with digital logic in the same die is becoming a standard for next generation processor power delivery. The input voltage of these regulators exceed well beyond the maximum voltage rating of the digital t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c4f69536454df2f938cce567fc0c650a
https://doi.org/10.1109/tcsii.2020.2981129
https://doi.org/10.1109/tcsii.2020.2981129
Autor:
Himanshu Kaul, Mark A. Anders, Vikram B. Suresh, Steven K. Hsu, Sanu Mathew, Gregory K. Chen, Sudhir K. Satpathy, Raghavan Kumar, Ram Krishnamurthy, Amit Agarwal, Monodeep Kar, Vivek De
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:945-955
Cryptographic circuits such as advanced encryption standard (AES) are vulnerable to correlation power analysis (CPA) side-channel attacks (SCAs), where an adversary monitors chip supply current signatures or electromagnetic (EM) emissions to decipher
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7308ed5dee4f0636f0d46b3079081c7d
https://doi.org/10.1109/jssc.2019.2960482
https://doi.org/10.1109/jssc.2019.2960482
Autor:
Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay, Venkata Chaitanya Krishna Chekuri, Monodeep Kar
Publikováno v:
IEEE Transactions on Power Electronics. 35:3242-3253
This article demonstrates all-digital tuning and dynamic control of feedback compensator in digital low drop out regulators to enhance the transient performance under process and passive variations, aging, and load changes. The measured results from
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ddf158a02526553ba3759bca4eb90501
https://doi.org/10.1109/tpel.2019.2930490
https://doi.org/10.1109/tpel.2019.2930490
Autor:
Monodeep Kar, Anand Rajan, Sanu Mathew, Venkata Chaitanya Krishna Chekuri, Vivek De, Arvind Singh, Saibal Mukhopadhyay
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:478-493
This article demonstrates enhanced power (P) and electromagnetic (EM) side-channel analysis (SCA) attack resistance of standard (unprotected) 128-bit advanced encryption standard (AES) engines with parallel (P-AES, 128-bit) and serial (S-AES, 8-bit)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d7ac550d8390a68c5dec2deab32d0559
https://doi.org/10.1109/jssc.2019.2945944
https://doi.org/10.1109/jssc.2019.2945944
Autor:
Himanshu Kaul, Amit Agarwal, Seongjong Kim, Knag Phil, Steven K. Hsu, Mark A. Anders, Gregory K. Chen, H. Ekin Sumbul, Ram Krishnamurthy, Raghavan Kumar, Monodeep Kar
Publikováno v:
IEEE Solid-State Circuits Letters. 3:118-121
A 10-nm compute-near-memory (CNM) accelerator augments SRAM with multiply accumulate (MAC) units to reduce interconnect energy and achieve 2.9 8b-TOPS/W for matrix–vector computation. The CNM provides high memory bandwidth by accessing SRAM subarra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ca80eb2340aca3ba2581bc6976662e34
https://doi.org/10.1109/lssc.2020.3007185
https://doi.org/10.1109/lssc.2020.3007185
Autor:
Ram Krishnamurthy, Sanu Mathew, Himanshu Kaul, H. Ekin Sumbul, Steven K. Hsu, Mark A. Anders, Raghavan Kumar, Vikram B. Suresh, Amit Agarwal, Vivek De, Seongjong Kim, Knag Phil, Gregory K. Chen, Monodeep Kar
Publikováno v:
IEEE Solid-State Circuits Letters. 3:338-341
A 10-nm DNN inference accelerator compresses model size with tabulation hash-based fine-grained weight sharing and increases 8b-compute density by $3.4\times $ to 1.6 TOPS/mm2. The compressed model DNN implements lightweight hashing circuits to compr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b4fe4e3893f358d725d82c17b2640f09
https://doi.org/10.1109/lssc.2020.3019349
https://doi.org/10.1109/lssc.2020.3019349
Autor:
Chen Liu, Monodeep Kar, Xueyang Wang, Nikhil Chawla, Neer Roggel, Bilgiday Yuce, Jason M. Fung
Publikováno v:
2021 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::443f53cbd356bd5fe78c9518e1d1ac0b
https://doi.org/10.1109/host49136.2021.9702271
https://doi.org/10.1109/host49136.2021.9702271
Autor:
Scot H. Rider, Martin Lutz, Moriyoshi Ohara, Pong-Fei Lu, Monodeep Kar, Xiao Sun, Kailash Gopalakrishnan, Jie Yang, Hoang Tran, Wei Wang, Michael A. Guillorn, Marcel Schaal, Ankur Agrawal, Xin Zhang, Joel Abraham Silberman, Sunil Shukla, Nianzheng Cao, James Bonano, Zhibin Ren, Sanchari Sen, Siyu Koswatta, Kyu-hyoun Kim, Mingu Kang, Swagath Venkataramani, Eri Ogawa, Vijayalakshmi Srinivasan, Hiroshi Inoue, Matt Ziegler, Howard M. Haynie, Shubham Jain, Vinay Velji Shah, Allison Allain, Jintao Zhang, Matthew Cohen, Jungwook Choi, Kerstin Schelm, Jinwook Oh, Li Yulong, Chia-Yu Chen, Ching Zhou, Naigang Wang, Jinwook Jung, Sae Kyu Lee, Silvia Melitta Mueller, Kazuaki Ishizaki, Bruce M. Fleischer, Michael R. Scheuermann, Vidhi Zalani, Brian W. Curran, Leland Chang, Mauricio J. Serrano, Ashish Ranjan, Alberto Mannari, Robert Casatuta
Publikováno v:
ISCA
The growing prevalence and computational demands of Artificial Intelligence (AI) workloads has led to widespread use of hardware accelerators in their execution. Scaling the performance of AI accelerators across generations is pivotal to their succes
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::edc72fc1439c98a561b7e0104cf8a62a
https://doi.org/10.1109/isca52012.2021.00021
https://doi.org/10.1109/isca52012.2021.00021