Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Monisa Ramesh Babu"'
Autor:
Parnashri Wankhede, Devansh Singh, Manish Kumar Sahu, Aruna Veluru, Monisa Ramesh Babu, Chenlong Miao, Shenghua Song, Shobhit Malik, Sriram Madhavan
Publikováno v:
DTCO and Computational Patterning.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc7fcc03896adebf99f30711acf38bfb
https://doi.org/10.1117/12.2614185
https://doi.org/10.1117/12.2614185
Autor:
Shenghua Song, Eric Chiu, Panneerselvam Venkatachalam, CT Lim, Chenlong Miao, Sriram Madhavan, William Wilkinson, Haizhou Yin, Shobhit Malik, Monisa Ramesh Babu, Peter Lin, Michael Wojtowecz, Deborah Ryan
Publikováno v:
2021 32nd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
At sub 14nm technology nodes, the ability to design, verify, and manufacture integrated circuits (IC) with high yield gain has become a major challenge. With the shrinking of semiconductor process technology, it is imperative for foundries to identif
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f451d018163ccbc244df6bb8763d8207
https://doi.org/10.1109/asmc51741.2021.9435661
https://doi.org/10.1109/asmc51741.2021.9435661
Autor:
Neerja Bawaskar, Fadi Batarseh, Davide Pacifico, Atul Chittora, Shenghua Song, Monisa Ramesh Babu, Shobhit Malik, Janam Bakshi
Publikováno v:
International Symposium for Testing and Failure Analysis.
Many fabless customers do not share the design information such as LEF/DEF (Library Exchange Format and Design Exchange Format), design netlist, and test program information with foundries because they contain proprietary IP. Determining the root-cau
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1eb74727b7dd90ec74ef311d74d9c631
https://doi.org/10.31399/asm.cp.istfa2020p0352
https://doi.org/10.31399/asm.cp.istfa2020p0352
Autor:
Joo Hyun Park, Deborah Ryan, Haizhou Yin, Pouya Rezaeifakhr, Shobhit Malik, Eric Chiu, Panneerselvam Venkatachalam, Kiruthika Murali, Praneetha Poluju, Shenghua Song, Sriram Madhavan, Monisa Ramesh Babu, Qian Xie
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XIV.
Semiconductor foundries typically analyze design layouts for criticality as a precursor to manufacturing flows. Risk assessment is performed on incoming layouts to identify and react to critical patterns at an early stage of the manufacturing cycle,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::79f9de1e6db1263bdcc99d042c7302e5
https://doi.org/10.1117/12.2551939
https://doi.org/10.1117/12.2551939