Two examples of approximate arithmetic to reduce hardware complexity and power consumption

Autor: Fornt Mas, Jordi, Jin, Leixin, Etxezarreta, Imanol, Fontova, Pau, Altet Sanahujes, Josep, Calomarde Palomino, Antonio, Morancho Llena, Enrique, Moll Echeto, Francisco de Borja, Rubio Sola, Jose Antonio

Publikováno v: 2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS).

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new c

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::000bc8a15f3c61a15e9c68b1d3b1c3f0
https://doi.org/10.1109/dcis55711.2022.9970160

Tunnel FET device characteristics for RF energy harvesting passive rectifiers

Autor: Nunes Cavalheiro, David Manuel, Moll Echeto, Francisco de Borja

Publikováno v: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
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The lack of high power conversion efficiency in RF passive rectifier circuits at sub-µW power levels with current MOSFET technologies is directly related with the difficulty of the transistors in conducting the required level of current at low volta

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::34196431a83a731cbf020c3ce49e045f
http://hdl.handle.net/2117/85309

Turtle logic: Novel IC digital probabilistic design methodology

Autor: García Leyva, Lancelot, Rubio Sola, Jose Antonio, Moll Echeto, Francisco de Borja, Calomarde Palomino, Antonio

Publikováno v: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname

Future electronic devices are expected to operate at lower voltage supply to save power, especially in ultimate and new technologies. The resulting reduction of logic levels approaches the thermal noise limit, and consequently signal to noise margins

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::dde0ab6ee462de9b9627209ccd19ea5e
http://hdl.handle.net/2117/11234

Variations-aware circuit designs for microprocessors

Autor: Pons Solé, Marc, Moll Echeto, Francisco de Borja, Abella Ferrer, Jaume

Publikováno v: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname

A new trend that is becoming dominant is to improve layout regularity so that the layouts to be printed are more repetitive and easy to manufacture. Our proposal is to push to the limit layout regularity to minimize manufacturing costs.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::5b049e07fba29e6404ae3e0f6505d113
http://hdl.handle.net/2117/11235

Energy macro-model for on chip interconnection buses

Autor: Mendoza Vázquez, Raymundo, Pons Solé, Marc, Moll Echeto, Francisco de Borja, Figueras, Joan

Publikováno v: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname

This report presents a fast method of evaluating the power consumption of a bus. Given an on-chip bus driver-interconnection-receiver design of N parallel lines,the objective is to develop its energy consumption macro-model. With this model we are be

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::4a133c304d02eefc71e01b65dcf115cf
https://hdl.handle.net/2117/1232