Výsledky vyhledávání - "Mohyar, Shaiful Nizam"

Conference

Architectural design proposal for real time clock for wireless microcontroller unit.

Autor: Mohd Alias, Muhammad Nor Azwan¹ azwan_mjg93@yahoo.com, Mohyar, Shaiful Nizam¹

Publikováno v: EPJ Web of Conferences. 2017, Vol. 162, p1-7. 7p. 6 Color Photographs, 9 Diagrams, 5 Charts.

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Akademický článek

On-chip temperature-based digital signal processing for customized wireless microcontroller

Autor: Faezal Siti Farhah Razanah, Md Isa Mohd Nazrin, Harun Azizi, Mohyar Shaiful Nizam, Jambek Asral Bahari

Publikováno v: EPJ Web of Conferences, Vol 162, p 01071 (2017)

Increases in die size and power density inside system-on-chip (SoC) design have brought thermal issue inside the system. Uneven heat-up and increasing in temperature offset on-chip has become a major factor that can limits the system performance. Thi

Externí odkaz: https://doaj.org/article/3f7b8871d535443b97b10f8f03a892eb

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Akademický článek

FPGA-based protein sequence alignment : A review

Autor: Md. Isa Mohd. Nazrin, Ku Muhsen Ku Noor Dhaniah, Saiful Nurdin Dayana, Ahmad Muhammad Imran, Zainol Murad Sohiful Anuar, Mohyar Shaiful Nizam, Harun Azizi, Hussin Razaidi

Publikováno v: EPJ Web of Conferences, Vol 162, p 01075 (2017)

Sequence alignment have been optimized using several techniques in order to accelerate the computation time to obtain the optimal score by implementing DP-based algorithm into hardware such as FPGA-based platform. During hardware implementation, ther

Externí odkaz: https://doaj.org/article/1d526cedc76f4dda8dd8827da725b4c9

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Design of a low-power CMOS operational amplifier with common-mode feedback for pipeline analog-to-digital converter applications

Autor: MURAD, SOHIFUL ANUAR ZAINOL, ISHAK, IZATUL SYAFINA, AHMAD, MOHD FAIRUS, MOHYAR, SHAIFUL NIZAM

Publikováno v: Volume: 25, Issue: 3 1908-1921
Turkish Journal of Electrical Engineering and Computer Science

This paper proposes a design of a low-power operational amplifier (op-amp) for pipeline analog-to-digital converter (ADC) applications using a 0.13-$\mu $m CMOS process. The folded-cascode topology with NMOS input types is employed for the op-amp des

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=tubitakulakb::d71f360b867c17c89747d70c5495d68a
https://dergipark.org.tr/tr/pub/tbtkelektrik/issue/35784/400521