Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Mohd Ziauddin Jahangir"'
Publikováno v:
Memories - Materials, Devices, Circuits and Systems, Vol 4, Iss , Pp 100052- (2023)
Digitally Controlled Oscillators (DCOs) are an integral part of All Digital Phase Locked Loops (ADPLLs). It is used to generate output frequency corresponding to the applied digital input. But, due to practical limitations in circuit design, DCOs res
Externí odkaz:
https://doaj.org/article/42324a884dd9453f9287766dbe893bfd
Publikováno v:
International Journal for Research in Applied Science and Engineering Technology. 10:377-386
Controller Area Network or CAN protocol is a method of communication between various electronic devices. It has significant use in the industry of automobiles. It defines a standard for efficient and reliable communication between sensor, actuator, c
Autor:
Mohd Ziauddin Jahangir
Publikováno v:
International Journal for Research in Applied Science and Engineering Technology. 10:5339-5351
Abstract In this article, a full custom design and implementation of a sine wave All Digital Phase Lock Loop (ADPLL) system based on ARM microcontroller is described. These ADPLL implementations are also referred as Software - Direct Digital Synthesi
Publikováno v:
2023 International Conference for Advancement in Technology (ICONAT).
Publikováno v:
2022 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT).
Publikováno v:
Lecture Notes in Electrical Engineering ISBN: 9789811955495
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8d10095aaeb7b6090fc9fef0590a98b3
https://doi.org/10.1007/978-981-19-5550-1_14
https://doi.org/10.1007/978-981-19-5550-1_14
Autor:
Mohd Ziauddin Jahangir, J. Mounika
Publikováno v:
Microelectronics Journal. 90:82-87
This work intends to prove that complex ternary combinational circuits can be custom designed using the conventional CMOS technology. This work focuses on implementing specific combinational circuits i.e. ternary 3 to 1 multiplexer circuit and Ternar
Publikováno v:
2017 International Conference on Computer, Electrical & Communication Engineering (ICCECE).
Branch predictors are implemented on pipelined CPUs having different types of instructions. Both unconditional and conditional branches are implemented utilizing different instruction set formats of the CPU. A basic pipelined CPU consists of three st
CMOS based design and simulation of ternary full adder and Ternary coded Decimal (TCD) adder circuit
Publikováno v:
2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT).
A number system with radix-3 is referred to as Ternary system. With a lot of new ternary circuits being proposed as an alternative to the digital logic, we take a step further, in this paper we propose to design a Ternary coded Decimal (TCD) adder ci
Publikováno v:
2015 Annual IEEE India Conference (INDICON).
Ternary logic can be more useful and efficient in the field of storing information. Ternary logic will give higher code capacity and can address large number of locations for fewer bits. Hence, Ternary logic can be used to store a greater amount of i