Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Mohamed Chentouf"'
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 9, Iss 1, p 3 (2019)
Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of
Externí odkaz:
https://doaj.org/article/950aee6f2f5541d1b990d7b7575343b7
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 7, Iss 4, p 25 (2017)
Power optimization is a very important and challenging step in the physical design flow, and it is a critical success factor of an application-specific integrated circuit (ASIC) chip. Many techniques are used by the place and route (P&R) electronic d
Externí odkaz:
https://doaj.org/article/fc95146bca764d60896e70bd9f242a4f
Publikováno v:
In Microelectronics Journal January 2019 83:147-154
Publikováno v:
Integration. 90:261-270
Publikováno v:
ACS Applied Electronic Materials. 5:846-857
Publikováno v:
Integration. 84:122-130
Publikováno v:
Integration. 76:13-24
Hold timing closure is an important milestone at the physical design phase of every Application Specific Integrated Circuit (ASIC). Many approaches have been proposed by different researchers and commercial Electronic Design Automation (EDA) provider
Publikováno v:
2021 International Conference on Microelectronics (ICM).
Publikováno v:
2021 International Conference on Microelectronics (ICM).
Publikováno v:
2021 IEEE/ACS 18th International Conference on Computer Systems and Applications (AICCSA).