Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Miyoshi Saito"'
Publikováno v:
Electronics and Communications in Japan (Part III: Fundamental Electronic Science). 88:1-11
In wireless communication environments such as indoors and in a relatively narrow region for which applications have recently started, the information transmission speed is sufficiently faster than the fading variation. In such cases, the fading vari
Publikováno v:
Physical Review B. 52:8244-8255
We report the numerical analysis of our experimental results for electron-wave propagation from a quantum point contact to a quantum wire. Our numerical method solves the boundary problem of a lattice model, and determines wave functions at an arbitr
Publikováno v:
Physical Review B. 46:13220-13233
Based on work by Molenkamp et al., we measured transfer efficiency through two quantum point contacts (QPC's) as a function of magnetic field applied perpendicularly to two-dimensional electron gas. We have reported that the results depend on the num
Publikováno v:
IEEJ Transactions on Electronics, Information and Systems. 110:749-758
Autor:
Iwao Sugiyama, Teruo Ishihara, Hideki Yoshizawa, Yuki Sakai, Seiichi Nishijima, Miyoshi Saito, Yoshio Hirose, Naoki Odate, Hisanori Fujisawa, Katsuhiro Yoda
Publikováno v:
2006 IEEE Asian Solid-State Circuits Conference.
Software defined radio (SDR) is expected to be a progressive technology for wireless communications under multi-communication systems. SDR requires high performance, low power consumption, and short latency hardware. We have developed a single-chip b
Publikováno v:
1996 Symposium on VLSI Circuits. Digest of Technical Papers.
We proposed a new sense-amplifier driver for low power, high-speed Gb-scale DRAMs. Our sense amplifier is temporally isolated from the bit line and we use overdriving with boost capacitors, to operate at a Vcc of down to 0.8 V. A charge recycle techn
Autor:
H. Araki, Miyoshi Saito, Kohtaroh Gotoh, Tsz-Shing Cheung, Junji Ogawa, Shigetoshi Wakayama, H. Tamura
Publikováno v:
1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).
We propose a fast row-cycle DRAM-core architecture, which employs temporal data storage buffers in the sense amplifier and pipelined row-address decoding. The temporal data storage buffers eliminated the restoring time and reduced the bit-line precha
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