Zobrazeno 1 - 10
of 33
pro vyhledávání: '"Mitsuhiro Togo"'
Autor:
Dou Xinyuan, Gu Sipeng, Bingwu Liu, Yanzhen Wang, Mitsuhiro Togo, Weihua Tong, Jae Gon Lee, Dongil Choi, Dibao Zhou, Jorge Argandona, Vidmantas Sargunas, Yong Yoong Hooi, Shashidhar Shintri, Hsien-Ching Lo
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 31:371-375
In this paper, CMOS wafer level ring oscillator frequency variability improvement >40% is demonstrated by either spatial source/drain activation or ion implantation super scan in FinFET technology. Yield improvement (up to 17%) is verified with bette
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0589aeb15fe975937227d109487c3cfa
https://doi.org/10.1109/tsm.2018.2847040
https://doi.org/10.1109/tsm.2018.2847040
Autor:
Seong Yeol Mun, Hong Yu, J. Versaggi, H. Wei, Alina Vinslava, C. Kyono, Jianwei Peng, Yue Hu, Hui Zhan, Xiaoli He, W.H. Chen, Yanzhen Wang, Baofu Zhu, Mitsuhiro Togo, Qi Yi, X. Zhang, M. Mohan, E. Lavigne, Owen Hu, Srikanth Samavedam, X. Dou, Jae Gon Lee, Dongil Choi, A. Sirman, Jinping Liu, D. K. Sohn, D. Kang, Ashish Kumar Jha, C. Gaire, Shi Yongjun, Zang Hui, Shen Yanping, Hsien-Ching Lo, Chloe Yong, X. Wan, Pei Zhao, D. Zhou
Publikováno v:
2018 IEEE Symposium on VLSI Technology.
We present a state-of-art 12LP FinFET technology with PPA (Performance, Power, and Area) improvement over 14LPP. 12LP enables >10% area reduction including a 7.5T library and 16% power reduction at fixed frequency or a 15% performance improvement at
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::23ed10354d4b7d67c3a786d4a647199d
https://doi.org/10.1109/vlsit.2018.8510632
https://doi.org/10.1109/vlsit.2018.8510632
Autor:
David Burnett, X. Zhang, E. Geiss, Ram Asra, El Mehdi Bazizi, Mitsuhiro Togo, H. Lazar, O. Kwon, Edmund Banghart, Jae Gon Lee, J. Versaggi, S. Yamaguchi, Owen Hu, D. K. Sohn, Palanivel Balasubramaniam, Srikanth Samavedam, Luigi Pantisano, Mohd Khair Hassan, H-C. Lo, B. Cohen, Hong Yu, H. S. Yang
Publikováno v:
2018 IEEE Symposium on VLSI Technology.
A multiple workfunction (multi-WF) integration technology was developed for ultra-low voltage operation in high performance FinFETs. It is essential to solve three key issues in the multi-WF process, a) short channel effect (SCE) degradation due to r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5d92781b198af435e6c309957973824a
https://doi.org/10.1109/vlsit.2018.8510641
https://doi.org/10.1109/vlsit.2018.8510641
Autor:
Scott Luning, Jon Kluth, Girish Bohra, Xiaobo Chen, Suraj K. Patil, Sherry Straub, Mitsuhiro Togo, Dina H. Triyoso, Anil Kumar, Alex Chen, Ryan Sporer, Kasun Punchihewa, Bob Mulfinger, Rohit Pal, X. Zhang, Jeremy A. Wahl, Amy Child, Laegu Kang, Rick Carter
Publikováno v:
ECS Transactions. 69:103-110
After decades of research, high-k metal gate has been successfully integrated into CMOS starting with 45nm node. High-k can be integrated using gate first or gate last integration. To continue scaling, the industry has chosen two integration approach
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9574743996ec5e2c320cb27e5003f17b
https://doi.org/10.1149/06905.0103ecst
https://doi.org/10.1149/06905.0103ecst
Autor:
X. Zhang, Manfred Eller, Mitsuhiro Togo, Murali Kota, T. Shimizu, Suraj K. Patil, Dina H. Triyoso, Suresh Uppal, Srikanth Samavedam, E. C. Silva, S. Dag, J. Lian, W. H. Tong, Y. Mamy Randriamihja
Publikováno v:
2016 IEEE Symposium on VLSI Technology.
A novel N/PFET threshold voltage (Vt) control scheme was developed for aggressive gate scaling. TiN plasma nitridation reduces absolute Vt by 100mV for both NFETs and PFETs at the same time without photolithography step increase and performance or re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f11a24b464e6077f496a6ebdfd20dbd
https://doi.org/10.1109/vlsit.2016.7573436
https://doi.org/10.1109/vlsit.2016.7573436
Autor:
Roger Loo, Jerome Mitard, Hugo Bender, Liesbeth Witters, Benjamin Vincent, Geert Hellings, Mitsuhiro Togo, Kristin De Meyer, S. Yamaguchi, Naoto Horiguchi, T. Chiarella, Andriy Hikavyy, An De Keersgieter, Nadine Collaert, Geert Eneman, Aaron Thean, Abdelkarim Mercha, Paola Favia, Anabela Veloso
Publikováno v:
ECS Transactions. 45:235-246
Novel device architectures offer improved scalability but come often at the price of increased layout sensitivity and a reduced or changed effectiveness of stressors and gate-last integration schemes. This work focuses on stress effects in n-type Fin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ef0249daa3c3c91f4bd9f344f8acd38b
https://doi.org/10.1149/1.3700889
https://doi.org/10.1149/1.3700889
Autor:
Manfred Eller, X. Zhang, Rohit Pal, Sruthi Muralidharan, Mitsuhiro Togo, Richard Carter, Srikanth Samavedam, Lakshmanan Vanamurthy, Yong Yoong Hooi
Publikováno v:
2015 IEEE International Electron Devices Meeting (IEDM).
This works examines the sources of electrical variation for FinFET technology based on silicon data from 90nm contacted poly pitch, dual-epitaxy, and RMG (replacement metal gate) transistor. A simple statistical model is used to predict electrical va
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c0dd909dbdd694734b34c803ba2d57d9
https://doi.org/10.1109/iedm.2015.7409748
https://doi.org/10.1109/iedm.2015.7409748
Autor:
Haruhiko Ono, Toru Tatsumi, Tohru Mogami, Koji Watanabe, Toyoji Yamamoto, Mitsuhiro Togo, Nobuyuki Ikarashi
Publikováno v:
IEEE Transactions on Electron Devices. 49:1903-1909
We have developed a low-leakage and highly reliable 1.5-nm SiON gate-dielectric by using radical oxygen and nitrogen. In this development, we introduce a new method for determining an ultrathin SiON gate-dielectric thickness based on the threshold vo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e466c6e3a805107e2c8d7d1f5010c27
https://doi.org/10.1109/ted.2002.804695
https://doi.org/10.1109/ted.2002.804695
Autor:
Mitsuhiro Togo, Shigeru Kimura, Tohru Mogami, Toru Tatsumi, M. Terai, Toyoji Yamamoto, Koji Watanabe
Publikováno v:
IEEE Transactions on Electron Devices. 49:1761-1767
We report the importance of oxynitridation using radical-oxygen and -nitrogen to form a low-leakage and highly reliable 1.6-nm SiON gate-dielectric without performance degradation in n/pFETs. It was found that oxidation using radical-oxygen forms hig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9e08d40515d300371bcab498a92d68e8
https://doi.org/10.1109/ted.2002.803640
https://doi.org/10.1109/ted.2002.803640
Autor:
Toru Tatsumi, Koji Watanabe, T. Fukai, M. Terai, Tohru Mogami, Toyoji Yamamoto, Mitsuhiro Togo
Publikováno v:
IEEE Transactions on Electron Devices. 49:1736-1741
We have demonstrated that oxynitridation using radical-oxygen (radical-O) and radical-nitrogen (radical-N) improves reverse narrow channel effects (RNCE) and reliability in sub-1.5-nm-thick gate-SiO/sub 2/ FETs with narrow channel and shallow-trench
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35e58fd778b50ec435b7a8b54c4a931d
https://doi.org/10.1109/ted.2002.802634
https://doi.org/10.1109/ted.2002.802634