Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Mitsuaki Hori"'
Publikováno v:
Microelectronics Reliability. 47:20-26
This work reviews the study of the chemical composition and the chemical structure of ultrathin oxynitride films using angle-resolved photoelectron spectroscopy. The nearest and the second nearest neighbors of a nitrogen atom in oxynitride films were
Publikováno v:
Microelectronic Engineering. 80:98-101
It was found by applying maximum entropy concept to angle-resolved Si 2p and N 1s photoelectron spectra that the distribution of nitrogen atoms and their bonding configurations in oxynitride films formed by nitridation of silicon oxide in nitrogen pl
Autor:
Makoto Yasuda, Taiji Ema, Kazushi Fujita, Mitsuaki Hori, M. Takahashi, M. Tsutsumi, H. Ogawa, Katsuaki Ookoshi
Publikováno v:
2013 IEEE International Electron Devices Meeting.
We have successfully embedded flash memory on an ultra-low power (
Autor:
M. Wojko, G. Krishnan, Vineet Agrawal, Mitsuaki Hori, S. Wakayama, Samuel Leshner, T. Yamada, Taiji Ema, J. Mitani, D. Zhao, T. Bakishev, Lawrence T. Clark, T. Tsuruta, S. Moriwaki, N. Kepler, Robert Rogenmoser, Pushkar Ranade, R. Roy, David A. Kidd
Publikováno v:
CICC
An SoC with ARM® Cortex™-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted Channel™ (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MH
A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits
Autor:
J. Mitani, T. Bakhishev, Taiji Ema, Y. Liu, D. Zhao, M. Duane, Yasunobu Torii, Kazushi Fujita, Y. Asada, D. Kidd, H. Ahn, Mitsuaki Hori, Thomas Hoffmann, J. Nagayama, L. Scudder, S. Pradhan, L. T. Clark, R. Rogenmoser, P. Gregory, S. Lee, D. Kanai, M. Wojko, Scott E. Thompson, Lucian Shifren, Pushkar Ranade, E. Boling
Publikováno v:
2012 International Electron Devices Meeting.
65nm Deeply Depleted Channel (DDCTM) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (V T ) variation, lower supply voltage (V CC ), enhanced body effect and I EFF . Digital circuits
Autor:
Mitsuaki Hori, Kenichi Okabe, J. Oh, M. Nakagawa, Scott E. Thompson, M. Kuramae, Toshiki Miyake, Taiji Ema, Lucian Shifren, Kazushi Fujita, Yasunobu Torii, Pushkar Ranade, T. Tsuruta, K. Ohkoshi, Toshihiko Mori
Publikováno v:
2011 International Electron Devices Meeting.
We have achieved aggressive reduction of V T variation and V DD-min by a sophisticated planar bulk MOSFET named ‘Deeply Depleted Channel ™ (DDC)’. The DDC transistor has been successfully integrated into an existing 65nm CMOS platform by combin
Autor:
Chioko Kaneta, Katsuto Tanahashi, Naoyoshi Tamura, Tsunehisa Sakoda, Tomohiro Kubo, Toshifumi Mori, Katsuji Ono, Yasuo Nara, Yoshiharu Tosaka, K. Hashimoto, Keita Nishigaya, Masataka Kase, Mitsuaki Hori, Hideya Matsuyama, Yuko Kobayashi, Hiroshi Minakata, Hiroko Mori
Publikováno v:
2010 IEEE International Reliability Physics Symposium.
In this paper, we have investigated bulk trap and interface trap density (D it ) caused by millisecond annealing (MSA) using gate current fluctuation (GCF) and charge pumping measurements. We show that the high energy flash lamp annealing (FLA) creat
Autor:
Mitsuaki Hori, Hiroshi Morioka, Y. Hayami, H. Mori, Akira Katakami, Kazuo Kawamura, Tamotsu Owada, Y. Shimamune, Naoyoshi Tamura, Takanobu Watanabe, Y. S. Kim, Hiroyuki Ohta, J. Ogura, Akiyoshi Hatada, K. Hashimoto, M. Kojima, T. Sakuma, Masashi Shima
Publikováno v:
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
Aggressively scaled 30nm gate CMOSFETs for 45nm node is reported. We successfully improved a higher drive current with keeping the short channel effect by Sigma shaped SiGe-source/drain (Sigma SiGe) structure using compressive-stressed liner. In addi
Autor:
Hideyuki Okamoto, Masataka Kase, Mitsuaki Hori, S. Shinagawa, Tetsuya Ikuta, Takeo Hattori, Hiroshi Nohira
Publikováno v:
Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials.
Autor:
Mitsuaki Hori, H. Kokura, K. Hashimoto, Manabu Kojima, Masataka Kase, Y. Tagawa, Y. Momiyama, Hiroshi Morioka, Toshihiro Sugii, Hiroyuki Ohta, S. Inagaki, Sergey Pidin, Toshihiko Mori, K. Goto, Naoyoshi Tamura
Publikováno v:
IEEE International Electron Devices Meeting 2003.
Aggressively scaled 25 nm gate CMOSFETs for the 65 nm node are reported. We successfully improved the short channel effect while keeping a high drive current by using total process controls (SW, offset-spacer, extension, halo, mechanical stress, etc.