Zobrazeno 1 - 10
of 42
pro vyhledávání: '"Miroslaw Chmiel"'
Publikováno v:
Applied Sciences, Vol 11, Iss 21, p 10183 (2021)
The article discusses counters defined in the IEC 61131-3 standard. The possible implementations of standard counters function blocks in FPGAs are presented. First, counters are implemented as classical hardware-based modules. Second, counters are de
Externí odkaz:
https://doaj.org/article/78b598c90b95431c88c62d8ff0c0a080
Autor:
Miroslaw Chmiel
Publikováno v:
Microprocessors and Microsystems. 65:37-46
This article discusses the possibilities of using FPGAs in order to construct fast PLCs that execute serial-cyclic program control loop. The PLCs bistable function blocks of the IEC 61131-3 standard with particular emphasis on the possible FPGA imple
Autor:
Robert Czerwinski, Miroslaw Chmiel
Publikováno v:
Electronics
Volume 8
Issue 12
Volume 8
Issue 12
This article discusses edge detectors implemented in programmable logic controllers. The behaviors of different vendors&rsquo
solutions are presented with pros and cons. The trigger functions defined in the IEC 61131-3 standard were analyzed for
solutions are presented with pros and cons. The trigger functions defined in the IEC 61131-3 standard were analyzed for
Publikováno v:
Problemy Mechatroniki, Vol 14, Iss 2, Pp 127-136 (2023)
For two decades, AREX Sp. z o.o. (Gdynia, Poland), belonging to WB Group (Warsaw, Poland), has been dealing with special-purpose production, in particular mechatronics, and its solutions are used in electromechanical accessories for 155 mm KRAB gun-h
Externí odkaz:
https://doaj.org/article/f08f5297b5754d53af03c0cc30d0f1b1
Publikováno v:
Microprocessors and Microsystems. 44:28-37
The paper discusses the design process of a programmable logic controller implemented by means of an FPGA device. The PLC implements on the machine language level a subset of the instruction set defined in the EN 61131-3 norm. Different aspects of in
Publikováno v:
Bulletin of the Polish Academy of Sciences Technical Sciences. 64:161-170
The paper presents an original idea of the selective control program execution that allows significant response time reduction. The exhaustive analysis of the PLC program performance is given. An analytic approach explains the idea of the selective c
Publikováno v:
IFAC-PapersOnLine. 49:454-459
The article discusses the design process of the central processing unit (CPU) for programmable logic controllers. On the one hand the designed CPU is compatible with IEC 61131-3 standard. On the other hand, the authors attempt to reflect on the possi
Publikováno v:
IFAC-PapersOnLine. 48:374-379
The paper discusses the design process of a programmable logic controller implemented by means of FPGA device. Designed PLC is to be compliant with EN 61131-3 standard. Diiferent aspects of instruction list and hardware architecture designing are pre
Publikováno v:
IFAC-PapersOnLine. 48:460-465
The paper presents the Arithmetic and Logic Unit (ALU) of a prototype Programmable Logic Controller (PLC), implemented in an FPGA device. The PLC implements on the machine language level a subset of the instruction set defined in the EN 61131-3 norm.
Publikováno v:
International Journal of Electronics and Telecommunications. 60:33-38
The paper presents considerations on implementation of function blocks of the IL language, as fragments of control programs that use these blocks. Subsequently, the predefined function blocks of the IL language have been applied to implementation in