Výsledky vyhledávání - "Miroslav Valka"

Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption

Autor: Ernesto Sanchez, Miroslav Valka, Luigi Dilillo, Matteo Sonza Reorda, Mauricio de Carvalho, Paolo Bernardi, Patrick Girard, Alberto Bosio

Publikováno v: Journal of Low Power Electronics
Journal of Low Power Electronics, American Scientific Publishers, 2013, 9 (2), pp.253-263. ⟨10.1166/jolpe.2013.1259⟩

International audience; High power consumption during test may lead to yield loss and premature aging. In particular, excessive peak power consumption during at-speed delay fault testing represents an important issue. In the literature, several techn

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::298d01c4a888a260e58857488bb739f3
https://doi.org/10.1166/jolpe.2013.1259

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Design for Test and Diagnosis of Power Switches

Autor: Miroslav Valka, Patrick Girard, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Stéphane Guilhot, Philippe Debaud

Publikováno v: Journal of Circuits, Systems, and Computers
Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2016, 25 (3), pp.1640013. ⟨10.1142/S0218126616400132⟩

International audience; Power gating techniques have been adopted so far to reduce the static power consumption of integrated circuits (ICs). Power gating is usually implemented by means of several power switches (PSs). Manufacturing defects affectin

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2939939e9d5e15ba0a66739bd8e52c9f
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01272986

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High Frequency Jitter Estimator for SoCs

Autor: Miroslav Valka, Herve Le Gall, Emmanuel Simeu, Haralampos-G. Stratigopoulos, Salvador Mir, Rshdee Alhakim

Publikováno v: 20th IEEE European Test Symposium (ETS'15)
20th IEEE European Test Symposium (ETS'15), May 2015, Cluj-Napoca, Romania
ETS

International audience; Best Paper Award This paper presents an Embedded Test Instrument (ETI) for the estimation of the High Frequency (HF) jitter of an observed clock signal. The ETI uses a second reference clock for under-sampling the observed sig

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::39080dd968d84f348f8c430f69cd65d9
https://hal.archives-ouvertes.fr/hal-01393415

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Design-for-Diagnosis Architecture for Power Switches

Autor: Patrick Girard, Stéphane Guilhot, Alberto Bosio, Philippe Debaud, Luigi Dilillo, Miroslav Valka, Arnaud Virazel

Publikováno v: 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems
DDECS: Design and Diagnostics of Electronic Circuits and Systems
DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2015, Belgrade, Serbia. pp.43-48, ⟨10.1109/DDECS.2015.18⟩
DDECS

International audience; Power-gating techniques have been adopted so far to reduce the static power consumption of an Integrated Circuit (IC). Power-gating is usually implemented by means of several power switches. Manufacturing defects affecting pow

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::240f17dbdfa2e1a1216a7704198c730e
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01272684

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iBoX — Jitter based Power Supply Noise sensor

Autor: A. Todri, Philippe Debaud, Stéphane Guilhot, Patrick Girard, Miroslav Valka, Arnaud Virazel, Alberto Bosio, Luigi Dilillo

Publikováno v: ETS

In this paper we propose a novel Power Supply Noise (PSN) sensor. It is based on timing uncertainty measure. Compared to state of the art it allows to measure the PSN events in more accurate way. The proposed sensor is actually under validation and p

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a73b82af5de84bb8073d51e6724a9c5e
https://doi.org/10.1109/ets.2014.6847830

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Test and diagnosis of power switches

Autor: Philippe Debaud, Stéphane Guilhot, Miroslav Valka, Luigi Dilillo, Arnaud Virazel, Alberto Bosio, Patrick Girard, A. Todri

Publikováno v: 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems
DDECS: Design and Diagnostics of Electronic Circuits and Systems
DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.213-218, ⟨10.1109/DDECS.2014.6868792⟩
DDECS

International audience; Power-gating techniques have been adopted so far to reduce the static power consumption of an Integrated Circuit (IC). Power gating is usually implemented by means of several power switches. Manufacturing defects affecting pow

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::95026409132b5fbc599685296e483087
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01248590

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Peak Power Estimation: A Case Study on CPU Cores

Autor: Patrick Girard, Paolo Bernardi, Alberto Bosio, Ernesto Sanchez, M. Sonza Reorda, Luigi Dilillo, Miroslav Valka, M. de Carvalho

Publikováno v: IEEE Asian Test Symposium
IEEE Asian Test Symposium, Nov 2012, Niigata, Japan. pp.167-172, ⟨10.1109/ATS.2012.58⟩
Asian Test Symposium

International audience; High peak power consumption during test may lead to yield loss. On the other hand, reducing too much test power may lead to test escape. In order to overcome this problem, test power has to mimic the power consumed during func

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7d2c8a28321f9967bed12744c4290893
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00805389

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Power Supply Noise Sensor Based on Timing Uncertainty Measurements

Autor: Patrick Girard, Alberto Bosio, A. Todri, Luigi Dilillo, Stéphane Guilhot, Miroslav Valka, Philippe Debaud, Arnaud Virazel

Publikováno v: Asian Test Symposium
21st IEEE Asian Test Symposium
ATS: Asian Test Symposium
ATS: Asian Test Symposium, Nov 2012, Niigata, Japan. pp.161-166, ⟨10.1109/ATS.2012.46⟩

International audience; In this work, we present a new power supply noise sensor based on timing uncertainty measurements. The proposed sensor can detect power supply noise events in a more accurate way compared to the state of the art solutions. Exp

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f147ed2446e3d182ad6e5c1ffa89cc58
https://doi.org/10.1109/ats.2012.46

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Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector

Autor: Miroslav Valka, Arnaud Virazel, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch

Publikováno v: DFT'11: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
DFT'11: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Vancouver, Canada. pp.N/A
DFT

In a radiating harsh environment, a distributed neutron sensor needs a robust data transfer infrastructure, since the latter is exposed to radiations as well as the sensing elements. In this paper, we present the architecture of a communication frame

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3139c1055b6d0816940ade9e4ba8dc66
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00651226

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