Zobrazeno 1 - 10
of 50
pro vyhledávání: '"Miroslav N. Velev"'
Autor:
Wei Zhang, Poki Chen, Naehyuck Chang, Eren Kursun, Makoto Nagata, M. Elfadel, Huawei Li, Partha Pratim Pande, Tae-Hyoung Kim, Ioannis Savidis, Houman Homayoun, Krishnendu Chakrabarty, Yuh-Shyan Hwang, Chirn Chye Boon, Patrick Mercier, Shih-Chieh Chang, Arun Natarajan, Chip-Hong Ho, Maxime Baas, Sheldon X.-D. Tan, Said Hamdioui, Mingoo Seok, Mehran Mozaffari Kermani, Aida Todri-Sanial, Koji Nii, Jaydeep P. Kulkarni, Masanori Hashimoto, Tsung-Yi Ho, Pasquale Corsonello, Massimo Alioto, Masud H. Chowdhury, Chulwoo Kim, Meng-Fan Chang, Hai Helen Li, Tanay Tan, Yao-Wen Chang, M. Tehranipoor, Prabhat Mishra, Stacey Weber Jackson, Zhengya Zhang, Rajiv L Joshi, Erik G. Larsson, Jiang Xu, Miroslav N. Velev
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:1-20
As I start my second two-year term (2017–2018) as the Editor-in-Chief (EIC) of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI), I wish the TVLSI readership a very happy new year and continued professional success. It gives me
Autor:
Prab Varma, Miroslav N. Velev
Publikováno v:
2016 IEEE International High Level Design Validation and Test Workshop (HLDVT).
Autor:
Miroslav N. Velev
Publikováno v:
Proceedings of the 26th edition on Great Lakes Symposium on VLSI.
Autor:
Miroslav N. Velev
Publikováno v:
Proceedings of the 25th edition on Great Lakes Symposium on VLSI.
Publikováno v:
ISQED
We present industrial experience on software health monitoring. Our goal was to determine whether we can predict abnormal behavior, based on data captured from software system interfaces. To analyze the system state and predict software health proble
Autor:
Miroslav N. Velev
Publikováno v:
IEEE Transactions on Education. 48:216-222
This paper presents a sequence of three projects on design and formal verification of pipelined and superscalar processors: 1) a single-issue, five-stage DLX (an academic processor used widely for teaching pipelined execution and defined by Hennessy
Autor:
Randal E. Bryant, Miroslav N. Velev
Publikováno v:
Journal of Symbolic Computation. 35:73-106
We compare SAT-checkers and decision diagrams on the evaluation of Boolean formulae produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. The microprocessors are described in a high-level hard
Autor:
Miroslav N. Velev, Ping Gao
Publikováno v:
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
Autor:
Ping Gao, Miroslav N. Velev
Publikováno v:
ISQED
We study the efficient formal verification of polymorphic heterogeneous multi-core architectures, such as Bahurupi, and also present insights on how to design such architectures at a high level of abstraction in order to facilitates their formal veri
Autor:
Miroslav N. Velev, Ping Gao
Publikováno v:
ASP-DAC
We present parallel algorithms for Binary Decision Diagram (BDD) manipulation optimized for efficient execution on Graphics Processing Units (GPUs). Compared to a sequential CPU-based BDD package with the same capabilities, our GPU implementation ach