Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Miodrag Vujkovic"'
Publikováno v:
ISCAS
This paper examines parallel multiplier architectures with respect to post-layout energy and delay. Our energy-delay analysis applied to several schemes takes into account the architectural as well as practical circuit implementation issues. Incorpor
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540290131
PATMOS
PATMOS
We have developed a complete design flow from Verilog/VHDL to layout that generates what is effectively a post-layout power versus delay curve for a digital IC block. Post-layout timing convergence is rapid over the entire delay range spanned by a po
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::21dcef3b2b8f0f6a5f8c3880b62bfa2c
https://doi.org/10.1007/11556930_41
https://doi.org/10.1007/11556930_41
Autor:
Miodrag Vujkovic, Carl Sechen
Publikováno v:
ICCAD
An effective way to compare logic techniques, logic families, or cell libraries is by means of power (or area) versus delay plots, since the efficiency of achieving a particular delay is of crucial significance. In this paper we describe a method of