Zobrazeno 1 - 2
of 2
pro vyhledávání: '"Minzhen Ren"'
Autor:
Taigon Song, Guanhao Shen, Ho Choi, Shreepad Panth, Dong Hyuk Woo, Young-Joon Lee, Moongon Jung, Ilya Khorosh, Gokul Kumar, Chang Liu, Mohammad M. Hossain, Michael B. Healy, Krit Athikulwongse, Sung Kyu Lim, Mohit Pathak, Minzhen Ren, Dean L. Lewis, Xin Zhao, Joungho Kim, Tzu-Wei Lin, Hsien-Hsin S. Lee, Gabriel H. Loh, Dae Hyun Kim
Publikováno v:
IEEE Transactions on Computers. 64:112-125
This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technol
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3381e1f4d4b71a283205e0b3f0214ab8
https://doi.org/10.1109/tc.2013.192
https://doi.org/10.1109/tc.2013.192
Autor:
Xin Zhao, Shreepad Panth, Ho Choi, Dae Hyun Kim, Young-Joon Lee, Dong Hyuk Woo, Joungho Kim, Hsien-Hsin Lee, Gokul Kumar, Tzu-Wei Lin, Michael B. Healy, Sung Kyu Lim, Mohammad M. Hossain, Krit Athikulwongse, Mohit Pathak, Minzhen Ren, Ilya Khorosh, Guanhao Shen, Taigon Song, Moongon Jung, Dean L. Lewis, Gabriel H. Loh, Chang Liu
Publikováno v:
Design for High Performance, Low Power, and Reliable 3D Integrated Circuits ISBN: 9781441995414
ISSCC
ISSCC
Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1–4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacke
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::90160ed98870eb2eb535e6145da52fa7
https://doi.org/10.1007/978-1-4419-9542-1_20
https://doi.org/10.1007/978-1-4419-9542-1_20
