Zobrazeno 1 - 10 of 18 pro vyhledávání: '"Ming-Yan Tsai"'
1
Akademický článek
A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications
Autor: Ming-Hwa Sheu, Chang-Ming Tsai, Ming-Yan Tsai, Shih-Chang Hsia, S. M. Salahuddin Morsalin, Jin-Fa Lin
Publikováno v: Sensors, Vol 21, Iss 19, p 6591 (2021)
An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (
Externí odkaz: https://doaj.org/article/224b45f9a21f47cba7c6b8aacfa84dd9
Zobrazit plný text záznamu
2
Akademický článek
A Novel Cross-Latch Shift Register Scheme for Low Power Applications
Autor: Po-Yu Kuo, Ming-Hwa Sheu, Chang-Ming Tsai, Ming-Yan Tsai, Jin-Fa Lin
Publikováno v: Applied Sciences, Vol 11, Iss 1, p 129 (2020)
The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occup
Externí odkaz: https://doaj.org/article/5bbb5a655f264fb7bddd558973f9ea83
Zobrazit plný text záznamu
3
Dissertation/ Thesis
none
Autor: Ming-Yan Tsai, 蔡名彥
107
This thesis is to investigate the gate characteristics of p-type GaN gated AlGaN/Ga N High Electron Mobility Transistor (HEMT), because p-type GaN can improve the energy barrier under the gate, effectively suppressing the gate current. It is
Externí odkaz: http://ndltd.ncl.edu.tw/handle/5r6a6r
Zobrazit plný text záznamu
4
Gate Capacitance and Off-State Characteristics of E-Mode p-GaN Gate AlGaN/GaN High-Electron-Mobility Transistors After Gate Stress Bias
Autor: Yu Chen Lai, Ming Yan Tsai, Yi Nan Zhong, Yue Ming Hsin
Publikováno v: Journal of Electronic Materials. 50:1162-1166
This study investigated the gate capacitance and off-state characteristics of 650-V enhancement-mode p-GaN gate AlGaN/GaN high-electron-mobility transistors after various degrees of gate stress bias. A significant change was observed in the on-state
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0d8ea1d59f5fceb16d0377ea0b1aab63
https://doi.org/10.1007/s11664-020-08691-w
Zobrazit plný text záznamu
5
A Novel Cross-Latch Shift Register Scheme for Low Power Applications
Autor: Jin-Fa Lin, Ming-Yan Tsai, Po-Yu Kuo, Chang-Ming Tsai, Ming-Hwa Sheu
Publikováno v: Applied Sciences
Volume 11
Issue 1
Applied Sciences, Vol 11, Iss 129, p 129 (2021)
The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occup
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9e5e3d84e656ed2dbc2d14ae0e596fe3
Zobrazit plný text záznamu
7
A novel low power flip-flop design using footless scheme
Autor: Jin-Fa Lin, Ming-Yan Tsai, Ching-Sheng Chang, Yu-Ming Tsai
Publikováno v: Analog Integrated Circuits and Signal Processing. 97:365-370
A low power true-single-phase clocking flip-flop (FF) design by using FootLess scheme named FLFF design targeting low VDD and low power operations is proposed. It is adapted from a recently presented FF design and achieves circuit simplification by u
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2acd3c116a9984871373ef6289b1726b
https://doi.org/10.1007/s10470-018-1327-x
Zobrazit plný text záznamu
9
Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes
Autor: Ming-Hwa Sheu, Jin-Fa Lin, Yin-Tsung Hwang, Ming-Yan Tsai, Chen-Syuan Wong
Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:3033-3044
In this paper, an ultralow-power true single-phase clocking flip-flop (FF) design achieved using only 19 transistors is proposed. The design follows a master–slave-type logic structure and features a hybrid logic design comprising both static-CMOS
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6c158b5f05872e31bc8181cb5f4c4ad8
https://doi.org/10.1109/tvlsi.2017.2729884
Zobrazit plný text záznamu
10
An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme
Autor: Jin-Fa Lin, Ming-Hwa Sheu, Ming-Yan Tsai, Po-Yu Kuo
Publikováno v: ISCAS
In this paper, an ultra-low-power true single-phase clocking flip-flop (FF) design is proposed. The design follows a master-slave-type logic structure and features a hybrid logic design comprising both static-CMOS logic and pass-transistor logic (PTL
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ec8f2228ee7d1af79a098802c2f1a0e3
https://doi.org/10.1109/iscas.2018.8350985
Zobrazit plný text záznamu

Vyhledávací nástroje:

Upřesnit hledání

Omezení vyhledávání
Plný text Recenzováno Digitální knihovna AV ČR
Zdroje