Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Ming-Shuan Chen"'
Autor:
Ming-Shuan Chen, 陳明軒
96
A full study of three data formats including duobinary, PAM4, and NRZ is proposed to estimate the performance of the corresponding transceivers under different conditions. Transceiver prototypes designed and optimized for the three signalings
A full study of three data formats including duobinary, PAM4, and NRZ is proposed to estimate the performance of the corresponding transceivers under different conditions. Transceiver prototypes designed and optimized for the three signalings
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/83613002706407803825
Autor:
Chih-Kong Ken Yang, Ming-Shuan Chen
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:1903-1916
This paper presents a complete 50–64 Gb/s serializing transmitter including a 4-tap equalizer. An LC-based FFE structure is proposed. The FFE improves the bandwidth of the delay line and the output combiner by applying the design methodology of LC-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8808b8f0ae6888013d5f8aa2fce87b44
https://doi.org/10.1109/jssc.2015.2411625
https://doi.org/10.1109/jssc.2015.2411625
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:763-775
A power-efficient transmitter is proposed using a multiphase serializer, multiphase dividers using injection-locked oscillators, and a high-speed multiplexing structure to relax the timing constraints. With this architecture, bit times near 1 FO-4 ga
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5a90df08688ae5486af6658e61a7e817
https://doi.org/10.1109/jssc.2015.2394323
https://doi.org/10.1109/jssc.2015.2394323
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:2681-2692
This paper presents a digital-to-phase converter (DPC) with 8-bits of resolution and a wide frequency range for the input/output clocks. A harmonic rejection (HR) filter is introduced to improve linearity across a frequency range of 0.1-1.5 GHz. Inst
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1e15ef85092ae4d4b0d569478d918c0a
https://doi.org/10.1109/jssc.2013.2274892
https://doi.org/10.1109/jssc.2013.2274892
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:627-640
This paper introduces a fully-integrated wireline transceiver operating at 40 Gb/s. The transmitter incorporates a 5-tap finite-inpulse response (FIR) filter with LC-based delay lines precisely adjusted by a closed-loop delay controller. The receiver
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f61efbd09e215140088b6327e17d5077
https://doi.org/10.1109/jssc.2011.2176635
https://doi.org/10.1109/jssc.2011.2176635
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:2120-2133
A full study of three data formats including duobinary, PAM4, and NRZ is proposed to estimate the performance of the corresponding transceivers under different conditions. Transceiver prototypes designed and optimized for the three signalings are pre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::798950c525d7dbb596c11fe9cfd260ed
https://doi.org/10.1109/jssc.2008.2001934
https://doi.org/10.1109/jssc.2008.2001934
Publikováno v:
VLSIC
This paper presents an improved repeater circuit that preserves the advantages of the inverter repeater and achieves a lower power, delay, and area by applying proper equalization. Designed and measured in 65nm CMOS technology, the proposed repeater
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cabe3ab02d69c8f9f3f897b8f3a0adc0
https://doi.org/10.1109/vlsic.2015.7231273
https://doi.org/10.1109/vlsic.2015.7231273
Autor:
Chih-Kong Ken Yang, Ming-Shuan Chen
Publikováno v:
CICC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::41212651f45dbc252c98c522db43c675
https://doi.org/10.1109/cicc.2014.6946020
https://doi.org/10.1109/cicc.2014.6946020
Publikováno v:
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).
This paper introduces the design of a high-speed reconfigurable analog-to-digital converter in 65-nm CMOS. Accuracy requirements are met without compromising performance by means of digital calibration and smart architecture selection. Partial interl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0dbc63e15437887c8b61b175d09a68a6
https://doi.org/10.1109/asscc.2013.6691038
https://doi.org/10.1109/asscc.2013.6691038
Publikováno v:
ISSCC
Serial-link transmitters are widely used in applications like optical transceivers and multi-gigabit Ethernet. At tens of Gb/s, the operating range of bit-rates is narrow; limited by the speed of the multiplexing and the setup and hold time constrain
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::17a0eb4a05047c6a2dcd2deafedc3c5a
https://doi.org/10.1109/isscc.2013.6487627
https://doi.org/10.1109/isscc.2013.6487627