Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Min-Sik Han"'
Autor:
Kyo-Won Jin, Park Min-Su, Kibong Koo, Dongkyun Kim, Jaein Lee, Hongjung Kim, Yongsung Lee, Geunho Choi, Sunmyung Choi, Min-Sik Han, Hankyu Chi, Sanghyun Ku, Kihun Kwon, Dong Uk Lee, Junhyun Chun, Byeongchan Choi, Jonghyuck Choi, Jun-Yong Song, Mingyu Park, Seungwook Oh, Yongmi Kim, Jong-sam Kim, Chang-Hyun Kim, Sungchun Jang, Im Da-In
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:167-177
A 1.1-V 6.4-Gb/s/pin 16-Gbit DDR5 is presented in 10-nm class CMOS technology. Various functions and circuits’ techniques are newly adopted to improve performance and power consumption compared with DDR4 SDRAM. First, to realize two times higher sp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e12e4dc4f05816d336bf381c790f6322
https://doi.org/10.1109/jssc.2019.2948806
https://doi.org/10.1109/jssc.2019.2948806
Autor:
Geunho Choi, Hongjung Kim, Dong Uk Lee, Jong-sam Kim, Jun-Yong Song, Jonghoon Oh, Im Da-In, Jang Sungchun, Jaein Lee, Jonghyuck Choi, Yongsung Lee, Haksong Kim, Chang-Hyun Lee, Jae-il Kim, Kyung-Whan Kim, Jinil Chung, Sunmyung Choi, Seo Young-Suk, Dae-Suk Kim, Chang-Hyun Kim, Sanghui Kim, Sanghyun Ku, Joo-Hwan Cho, Min-Sik Han, Seong-Hwi Song, Kihun Kwon, Hankyu Chi, Junhyun Chun, Yeon-Uk Kim, Seungwook Oh, Yongmi Kim, Byeongchan Choi, Dongkyun Kim, Park Min-Su, Kibong Koo
Publikováno v:
ISSCC
Required system performance for the computing and server, cost and power forces DRAM to improve its bandwidth, capacity and power. DDR5 SDRAM has been proposed as the next memory solution, with various new functions and circuit techniques to overcome
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8936055dd78872fd46b279b4cb482399
https://doi.org/10.1109/isscc.2019.8662320
https://doi.org/10.1109/isscc.2019.8662320
Publikováno v:
2009 International SoC Design Conference (ISOCC).
A high-speed differential receiver with low-power interleaved direct decision feedback equalizer (DFE) is proposed and designed with a 0.18 um CMOS process. To save the power consumption, the new feedback topology is introduced. This architecture fee
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::df55356afb6f5c632244fdd6f9838f0a
https://doi.org/10.1109/socdc.2009.5423824
https://doi.org/10.1109/socdc.2009.5423824
Publikováno v:
2009 International SoC Design Conference (ISOCC); 2009, p532-535, 4p