Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Min-Hao Chiu"'
Autor:
Min-Hao Chiu, 邱銘豪
93
This paper presents a Jump scan technique (or J-scan) for low power testing. The J-scan shifts two bits of scan data per clock cycle so the scan frequency is halved without increasing the test time. The experimental data show that the propose
This paper presents a Jump scan technique (or J-scan) for low power testing. The J-scan shifts two bits of scan data per clock cycle so the scan frequency is halved without increasing the test time. The experimental data show that the propose
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/52041775619598250286
Autor:
Chun-Chia Chen, Tsu-Ming Liu, Min-Hao Chiu, Tung-Hsing Wu, Chi-cheng Ju, Wei-Cing Li, Yen-Chieh Lai, Yi-Hsin Huang, Peng-Hao Wang, Yen-Chao Huang, Chih-Ming Wang, Ping Chao, Hsiu-Yi Lin, Ming-Long Wu, Meng-Jye Hu, Yu-Kun Lin, Ting-An Lin, Chia-Yun Cheng, Che-Hong Chen, Sheng-Jen Wang, Shun-Hsiang Chuang, Han-Liang Chou, Chen Lien-Fei, Hue-Min Lin, Yung-Chang Chang, Chih-Da Chien, Kun-bin Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:56-67
A 4 K $\,\times\,$ 2 K H.265/HEVC video codec chip supporting 14 video standard formats is implemented on a 1.49 $\,\times\,$ 1.45 mm $^{2}$ die in a 28 nm CMOS process. Several HEVC fast algorithms reduce the coding modes by analyzing the content fe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4237a07f3493efd5831e6195d5e3fa3a
https://doi.org/10.1109/jssc.2015.2465857
https://doi.org/10.1109/jssc.2015.2465857
Autor:
Hsiao-En Chen, Ping Chao, Min-Hao Chiu, Hue-Min Lin, Chen Yi-Chang, Hsiu-Yi Lin, Chih-Wen Yang, Yung-Chang Chang, Shun-Hsiang Chuang, Meng-Jye Hu, Chi-cheng Ju, Chia-Yun Cheng, Fu-Chun Yeh, Che-Hong Chen, Peng Hsuan-Wen, Sheng-Jen Wang, Yenchieh Huang, Chun-Chia Chen, Chih-Ming Wang, Ming-Long Wu, Kao Chia-Hung, Tsu-Ming Liu, Chia-Lin Ho
Publikováno v:
ESSCIRC
A lower power and area efficient VP9 and multi-standard video decoder chip is first-reported for Android 4K TV. It supports prevalent MPEG-x, VP-x, RMx, WMV-x and H.26x series video standards in a single chip. Three high-throughput techniques, look-a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7893b0820d5c8154d5276c1b46d73542
https://doi.org/10.1109/esscirc.2016.7598254
https://doi.org/10.1109/esscirc.2016.7598254
Autor:
Chia-Lin Ho, Ping Chao, Hsiu-Yi Lin, Che-Hong Chen, Min-Hao Chiu, Hue-Min Lin, Chun-Chia Chen, Ming-Long Wu, Tsu-Ming Liu, Chia-Yun Cheng, Fu-Chun Yeh, Shun-Hsiang Chuang, Chi-cheng Ju, Chih-Ming Wang, Yung-Chang Chang, Sheng-Jen Wang, Meng-Jye Hu
Publikováno v:
ICME
A 4K and Main-10 HEVC video decoder LSI is fabricated in a 28nm CMOS process. It adopts a block-concealed processor (BcP) to improve the visual quality and a bandwidth-suppressed processor (BsP) is newly designed to reduce 30% and 45% of external dat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b78113c8934404e0f385c47dce568209
https://doi.org/10.1109/icme.2015.7177399
https://doi.org/10.1109/icme.2015.7177399
Autor:
Min-Hao Chiu, Yu-Kun Lin, Peng-Hao Wang, Tsu-Ming Liu, Yen-Chao Huang, Ping Chao, Kun-bin Lee, Han-Liang Chou, Hue-Min Lin, Chen Lien-Fei, Ryan Chen, Yung-Chang Chang, Ming-Long Wu, Kevin Jou, Wei-Cing Li, Yen-Chieh Lai, Yi-Hsin Huang, Che-Hong Chen, Tung-Hsing Wu, H Y Hsu, Sheng-Jen Wang, Chih-Da Chien, Ting-An Lin, Shun-Hsiang Chuang, Chun-Chia Chen, Chi-cheng Ju, Hsiu-Yi Lin, Chin-Ming Wang, Meng-Jye Hu, Chia-Yun Cheng, Fu-Chun Yeh
Publikováno v:
ISSCC
A 4K×2K H.265/HEVC video codec chip is fabricated in a 28nm CMOS process with a core area of 2.16mm2. This LSI chip integrates a dual-standard (H.265 and H.264) video codec and a series of prevalent (VC-1, WMV-7/8/9, VP-6/8, AVS, RM-8/9/10, MPEG-2/4
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::220b21ba0bbb83d403b694f7b2e5d1cb
https://doi.org/10.1109/isscc.2015.7063063
https://doi.org/10.1109/isscc.2015.7063063
Autor:
Min-Hao Chiu, Hsiu-Yi Lin, Che-Hong Chen, Chung-Hung Tsai, Chi-cheng Ju, Chia-Yun Cheng, Fu-Chun Yeh, Ping Chao, Tsu-Ming Liu, Chun-Chia Chen, Shun-Hsiang Chuang, Hue-Min Lin, Meng-Jye Hu, Chih-Ming Wang, Yung-Chang Chang, Ming-Long Wu, Sheng-Jen Wang
Publikováno v:
ESSCIRC
a first-reported 4Kx2K@60fps and Main-10 HEVC video decoder integrating 14 video formats is fabricated in a 28nm CMOS process. It adopts an Adaptive Coding Unit Balance (ACUB) and Data-Sharing Wave-front Dual-core (DSWD) architectures to lower the re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::54825c0c372422eeff6298bd26e53f2a
https://doi.org/10.1109/esscirc.2014.6942055
https://doi.org/10.1109/esscirc.2014.6942055
Autor:
Chun-Chia Chen, Ping Chao, Huaide Wang, Min-Hao Chiu, Chia-Yun Cheng, Chang-Lin Hsieh, Hue-Min Lin, Ryan Yeh, Chih-Ming Wang, Hsiu-Yi Lin, Chung-Hung Tsai, Ted Chuang, Yung-Chang Chang, Chi-cheng Ju, Tsu-Ming Liu, Sheng-Jen Wang, Brian Liu, Meng-Jye Hu
Publikováno v:
VLSIC
A first-reported 4K×2K@60fps digital TV SoC processor supporting 9 video formats and integrating HDMI/MHL receiver is fabricated in a 40nm CMOS process. It adopts error compensation processor (ECP) to improve the visual quality, and designs a memory
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8acff72431d8b3b839cfb286ade2fa3a
https://doi.org/10.1109/vlsic.2014.6858389
https://doi.org/10.1109/vlsic.2014.6858389
Autor:
Yung-Chang Chang, Min-Hao Chiu, Kun-bin Lee, Chi-cheng Ju, Yi-Hsin Huang, Chih-Ming Wang, Yi-Hau Chen, Han-Liang Chou, Sheng-Jen Wang, Hsueh-Te Chao, Tung-Hsing Wu, Yu-Kun Lin, Chun-Chia Chen, Tin-An Lin, Hue-Min Lin, Tsu-Ming Liu, Tsung-Chuan Ma, Cheng-Hung Liu, Chia-Yun Cheng, Wei-Cing Li, Chung-Hung Tsai
Publikováno v:
2012 IEEE Asian Solid State Circuits Conference (A-SSCC).
A first dual-standard video encoder and decoder LSI providing VP8 (i.e. video format of WebM project for use of web's video) or H.264/AVC video recording and playback simultaneously is implemented with 28nm CMOS and occupies 1.94mm2 of core area. Sev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::13821c7e7af4b566598d2b9c2fd9fa9b
https://doi.org/10.1109/ipec.2012.6522611
https://doi.org/10.1109/ipec.2012.6522611
Autor:
Tsu-Ming Liu, Chia-Yun Cheng, Hue-Min Lin, Te-Chi Hsiao, Chuang-Chi Chiou, Ginny Chen, Yeh-Lin Chu, Yuan-Chun Lin, Chi-cheng Ju, Chih-Ming Wang, Yung-Chang Chang, Pin-Huan Hsu, Chung-Hung Tsai, Bin-Jung Tsai, Chun-Chia Chen, Jiun-Yuan Wu, Sheng-Jen Wang, Min-Hao Chiu
Publikováno v:
ICME
a 3D Blu-ray-compliant multimedia processor integrating video decoder, display and graphic engines is presented. To cope with the bandwidth/cost-starved Blu-ray system, this design exploits the time-sharing techniques, leading to 31.3% and 29.1% of a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c4049a77677d84b40dbcebc2d718285e
https://doi.org/10.1109/icme.2012.81
https://doi.org/10.1109/icme.2012.81
Autor:
Ping Chao, Hue-Min Lin, Sheng-Jen Wang, Min-Hao Chiu, Chia-Yun Cheng, Tsu-Ming Liu, Chun-Chia Chen, Chi-cheng Ju, Chih-Ming Wang, Hao-Wei Li, Meng-Jye Hu, Yung-Chang Chang, Chung-Hung Tsai
Publikováno v:
ISCAS
A first-reported, sub-mW/fps/view multi-view video decoder chip fully compliant to 3D Blu-ray specifications is reported. It explores the resource sharing so as to integrate not only single-view MPEG-2/VC-1/AVC but multi-view MVC standards into a sin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::98d059a2fd3d52f5d780d6605c643528
https://doi.org/10.1109/iscas.2012.6271516
https://doi.org/10.1109/iscas.2012.6271516