Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Min-Da Hu"'
Publikováno v:
ECS Transactions. 80:279-285
Abstract—In advanced CMOS technology node with Cu/low-K interconnection, double patterning scheme with Metal Hard-Mask (MHM) All-In-One (AIO) etch is used to define smaller via and trench. The bottom profile of via is critical for via connectivity
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::57963fae25a8637e5923837f636a8718
https://doi.org/10.1149/08004.0279ecst
https://doi.org/10.1149/08004.0279ecst
Publikováno v:
2017 China Semiconductor Technology International Conference (CSTIC).
In advanced CMOS technology node with Cu/low-K interconnection, double patterning scheme with Trench First Metal Hard-Mask (TFMHM) approach All-In-One (AIO) etch is used to define smaller scale via and trench. The loading effect between different pat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2e1058c02b1d1abf89720745a5e160d7
https://doi.org/10.1109/cstic.2017.7919780
https://doi.org/10.1109/cstic.2017.7919780
Autor:
Hai-Yang Zhang, Dong-Jiang Wang, Min-Da Hu, Qiu-Hua Han, Huang Ruixuan, Huang Jingyong, Qi-Yang He, Xiao-jun Jiang, Xiao-Ying Meng
Publikováno v:
ECS Transactions. 60:355-360
Since CMOS technology moved to 28nm node and beyond, ArF immersion lithography process already reached its limitation from the point of view of line width roughness (LWR) and photo resist (PR) profile control. The majority of this work focused on the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::91076d8f1a3f3e2890d30b025cca8f9e
https://doi.org/10.1149/06001.0355ecst
https://doi.org/10.1149/06001.0355ecst
Publikováno v:
ECS Transactions. 60:343-347
Metal hard-mask based all-in-one etch scheme has been extensively integrated with Cu interconnects for its significant improvement in terms of the line sidewall roughness, the reduction of ultra low-k material damage and the enhancement of lithograph
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc18b152184b29990168bdb515f8c375
https://doi.org/10.1149/06001.0343ecst
https://doi.org/10.1149/06001.0343ecst
Publikováno v:
ECS Transactions. 52:349-355
This work mainly focuses on the post-etch treatment (PET) in dielectric etch processes from contact etch, trench etch to all-in-one etch. PET step is optimized not only to efficiently remove the byproducts formed on the sidewall/bottom of contact/via
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d7c9a9da8db790a961d770187fd0e58
https://doi.org/10.1149/05201.0349ecst
https://doi.org/10.1149/05201.0349ecst
Autor:
Hai-Yang Zhang, Fu Yali, Min-Da Hu, Dong-Jiang Wang, Cheng-Long Zhang, Jun-Qing Zhou, Wang Xinpeng
Publikováno v:
ECS Transactions. 52:365-370
Two patterning schemes and etch approaches were exploited to study the formation of TiN blade BEC (bottom electrical contact) from the reactive ion etch point of view. Patterning scheme I features the benefit of cost-saving but less scalability due t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0ab995515a68d01cc501a687402797ca
https://doi.org/10.1149/05201.0365ecst
https://doi.org/10.1149/05201.0365ecst
Autor:
Yi-Bin Cao, Siyuan Frank Yang, Wang Xinpeng, Dong-Jiang Wang, Jun-Qing Zhou, Hai-Yang Zhang, Min-Da Hu, Cheng-Long Zhang, Zheng-Hao Gan
Publikováno v:
ECS Transactions. 52:295-300
In this paper, we studied the improvement of EM lifetime distribution including both intrinsic lifetime extension and the reduction of earlier failure percentage by applying a uniform design of experiments (UDE) to organic under layer (OUL) step. UDE
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f6ab3ea4f38263015665e706589d262a
https://doi.org/10.1149/05201.0295ecst
https://doi.org/10.1149/05201.0295ecst
Autor:
Jun-Qing Zhou, Dong-Jiang Wang, Cheng-Long Zhang, Hai-Yang Zhang, Min-Da Hu, Wang Xinpeng, Kwok-Fung Lee
Publikováno v:
ECS Transactions. 52:325-330
Porous low-k dielectrics have been extensively integrated into back-end-of-line (BEOL) for its significant improvement of chip resistance-capacitance (RC) delay performance. However, Metal hard-mask (MHM) has to be introduced to reduce the low-k dama
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::72018284e8a3987639159ac0f7654783
https://doi.org/10.1149/05201.0325ecst
https://doi.org/10.1149/05201.0325ecst
Autor:
Qiyang He, Min-Da Hu, Linlin Sun, Xing-Hua Song, Kefang Yuan, Jun-Qing Zhou, Hai-Yang Zhang, Cao Yibin
Publikováno v:
2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).
In advanced CMOS technology nodes with Cu/low-k interconnect, metal hard-mask approach AIO etch is the key process to define the physical structure of Cu line and via. The via hole and via slot always land on lower metal Cu as design rule requested.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::37303c40526dbb53146f10dcb78f1b9f
https://doi.org/10.1109/iitc-amc.2016.7507713
https://doi.org/10.1109/iitc-amc.2016.7507713
Autor:
Da-Lin Yao, Hai-Yang Zhang, Qiyang He, Cheng-Long Zhang, Yuan Guangjie, Min-Da Hu, Jun-Qing Zhou
Publikováno v:
2016 China Semiconductor Technology International Conference (CSTIC).
Pulsed capacitively coupled plasmas (CCP) was applied to self-aligned-via (SAV) based all-in-one (AIO) etching process. Effects of bias and synchronous pulsed plasmas on the AIO etching process were analyzed to improve the reliability and reduce the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ca3ce19a844e633dbec389218c4876ed
https://doi.org/10.1109/cstic.2016.7463996
https://doi.org/10.1109/cstic.2016.7463996